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[AMDGPU] Fix scheduler live-ins with debug inst at start of block
GCNDownwardRPTracker RPTracker.reset() skips debug instructions for NextMI so RPTracker.getNext() will never give the beginning of a sched region if it is a debug value. In this case we will never set the live-ins for that block. Add check to see if getNext also equals the MI after skipping debug instructions. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D118853
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2 files changed

+70
-3
lines changed

2 files changed

+70
-3
lines changed

‎llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -493,14 +493,14 @@ void GCNScheduleDAGMILive::computeBlockPressure(const MachineBasicBlock *MBB) {
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auto I = MBB->begin();
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auto LiveInIt = MBBLiveIns.find(MBB);
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auto &Rgn = Regions[CurRegion];
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auto *NonDbgMI = &*skipDebugInstructionsForward(Rgn.first, Rgn.second);
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if (LiveInIt != MBBLiveIns.end()) {
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auto LiveIn = std::move(LiveInIt->second);
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RPTracker.reset(*MBB->begin(), &LiveIn);
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MBBLiveIns.erase(LiveInIt);
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} else {
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auto &Rgn = Regions[CurRegion];
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I = Rgn.first;
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auto *NonDbgMI = &*skipDebugInstructionsForward(Rgn.first, Rgn.second);
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auto LRS = BBLiveInMap.lookup(NonDbgMI);
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#ifdef EXPENSIVE_CHECKS
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assert(isEqual(getLiveRegsBefore(*NonDbgMI, *LIS), LRS));
@@ -511,7 +511,7 @@ void GCNScheduleDAGMILive::computeBlockPressure(const MachineBasicBlock *MBB) {
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for ( ; ; ) {
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I = RPTracker.getNext();
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if (Regions[CurRegion].first == I) {
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if (Regions[CurRegion].first == I || NonDbgMI == I) {
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LiveIns[CurRegion] = RPTracker.getLiveRegs();
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RPTracker.clearMaxPressure();
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}

‎llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
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# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# CHECK: ********** MI Scheduling **********
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# CHECK-NEXT: test_get_liveins:%bb.1
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# CHECK: Region live-in pressure: VGPRs: 1 AGPRs: 0, SGPRs: 0, LVGPR WT: 0, LSGPR WT: 0
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# CHECK: ScheduleDAGMILive::schedule starting
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---
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name: test_get_liveins
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tracksRegLiveness: true
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frameInfo:
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hasCalls: true
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body: |
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bb.0:
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successors: %bb.1
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%0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0
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bb.1:
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successors: %bb.2
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DBG_VALUE %0:vgpr_32, 0, 0
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%1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0
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%2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0
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%3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0
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%4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0
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%5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0
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%6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0
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%7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0
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%8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0
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%9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0
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%10:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode, implicit-def $m0
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%11:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode, implicit-def $m0
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%12:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode, implicit-def $m0
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%13:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode, implicit-def $m0
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%14:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode, implicit-def $m0
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%15:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode, implicit-def $m0
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%16:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode, implicit-def $m0
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%17:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode, implicit-def $m0
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%18:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode, implicit-def $m0
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%19:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0
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%20:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0
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%21:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0
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%22:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0
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%23:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode, implicit-def $m0
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%24:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode, implicit-def $m0
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bb.2:
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DBG_VALUE %24:vgpr_32, 0, 0
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S_NOP 0, implicit %0
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S_NOP 0, implicit %1, implicit %2
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S_NOP 0, implicit %3, implicit %4
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S_NOP 0, implicit %5, implicit %6
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S_NOP 0, implicit %7, implicit %8
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S_NOP 0, implicit %9, implicit %10
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S_NOP 0, implicit %11, implicit %12
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S_NOP 0, implicit %13, implicit %14
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S_NOP 0, implicit %15, implicit %16
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S_NOP 0, implicit %17, implicit %18
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S_NOP 0, implicit %19, implicit %20
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S_NOP 0, implicit %21, implicit %22
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S_NOP 0, implicit %23, implicit %23
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S_NOP 0, implicit %24
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S_ENDPGM 0
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...
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