Skip to content

Commit 592f52d

Browse files
mtrofinmtrofin
committed
[nfc][regalloc] const LiveIntervals within the allocator
Once built, LiveIntervals are immutable. This patch captures that. Differential Revision: https://reviews.llvm.org/D118918
1 parent 9fa3243 commit 592f52d

17 files changed

+204
-190
lines changed

‎llvm/include/llvm/CodeGen/LiveIntervalUnion.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ class LiveIntervalUnion {
4343
// A set of live virtual register segments that supports fast insertion,
4444
// intersection, and removal.
4545
// Mapping SlotIndex intervals to virtual register numbers.
46-
using LiveSegments = IntervalMap<SlotIndex, LiveInterval*>;
46+
using LiveSegments = IntervalMap<SlotIndex, const LiveInterval *>;
4747

4848
public:
4949
// SegmentIter can advance to the next segment ordered by starting position
@@ -88,10 +88,10 @@ class LiveIntervalUnion {
8888
bool changedSince(unsigned tag) const { return tag != Tag; }
8989

9090
// Add a live virtual register to this union and merge its segments.
91-
void unify(LiveInterval &VirtReg, const LiveRange &Range);
91+
void unify(const LiveInterval &VirtReg, const LiveRange &Range);
9292

9393
// Remove a live virtual register's segments from this union.
94-
void extract(LiveInterval &VirtReg, const LiveRange &Range);
94+
void extract(const LiveInterval &VirtReg, const LiveRange &Range);
9595

9696
// Remove all inserted virtual registers.
9797
void clear() { Segments.clear(); ++Tag; }
@@ -105,7 +105,7 @@ class LiveIntervalUnion {
105105
#endif
106106

107107
// Get any virtual register that is assign to this physical unit
108-
LiveInterval *getOneVReg() const;
108+
const LiveInterval *getOneVReg() const;
109109

110110
/// Query interferences between a single live virtual register and a live
111111
/// interval union.
@@ -114,7 +114,7 @@ class LiveIntervalUnion {
114114
const LiveRange *LR = nullptr;
115115
LiveRange::const_iterator LRI; ///< current position in LR
116116
ConstSegmentIter LiveUnionI; ///< current position in LiveUnion
117-
SmallVector<LiveInterval *, 4> InterferingVRegs;
117+
SmallVector<const LiveInterval *, 4> InterferingVRegs;
118118
bool CheckedFirstInterference = false;
119119
bool SeenAllInterferences = false;
120120
unsigned Tag = 0;
@@ -125,7 +125,7 @@ class LiveIntervalUnion {
125125
unsigned collectInterferingVRegs(unsigned MaxInterferingRegs);
126126

127127
// Was this virtual register visited during collectInterferingVRegs?
128-
bool isSeenInterference(LiveInterval *VirtReg) const;
128+
bool isSeenInterference(const LiveInterval *VirtReg) const;
129129

130130
public:
131131
Query() = default;
@@ -159,7 +159,7 @@ class LiveIntervalUnion {
159159
bool checkInterference() { return collectInterferingVRegs(1); }
160160

161161
// Vector generated by collectInterferingVRegs.
162-
const SmallVectorImpl<LiveInterval *> &interferingVRegs(
162+
const SmallVectorImpl<const LiveInterval *> &interferingVRegs(
163163
unsigned MaxInterferingRegs = std::numeric_limits<unsigned>::max()) {
164164
if (!SeenAllInterferences || MaxInterferingRegs < InterferingVRegs.size())
165165
collectInterferingVRegs(MaxInterferingRegs);

‎llvm/include/llvm/CodeGen/LiveIntervals.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -374,7 +374,7 @@ class VirtRegMap;
374374
///
375375
/// Returns false if \p LI doesn't cross any register mask instructions. In
376376
/// that case, the bit vector is not filled in.
377-
bool checkRegMaskInterference(LiveInterval &LI,
377+
bool checkRegMaskInterference(const LiveInterval &LI,
378378
BitVector &UsableRegs);
379379

380380
// Register unit functions.

‎llvm/include/llvm/CodeGen/LiveRangeEdit.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ class LiveRangeEdit : private MachineRegisterInfo::Delegate {
6666
};
6767

6868
private:
69-
LiveInterval *Parent;
69+
const LiveInterval *const Parent;
7070
SmallVectorImpl<Register> &NewRegs;
7171
MachineRegisterInfo &MRI;
7272
LiveIntervals &LIS;
@@ -129,7 +129,7 @@ class LiveRangeEdit : private MachineRegisterInfo::Delegate {
129129
/// be done. This could be the case if called before Regalloc.
130130
/// @param deadRemats The collection of all the instructions defining an
131131
/// original reg and are dead after remat.
132-
LiveRangeEdit(LiveInterval *parent, SmallVectorImpl<Register> &newRegs,
132+
LiveRangeEdit(const LiveInterval *parent, SmallVectorImpl<Register> &newRegs,
133133
MachineFunction &MF, LiveIntervals &lis, VirtRegMap *vrm,
134134
Delegate *delegate = nullptr,
135135
SmallPtrSet<MachineInstr *, 32> *deadRemats = nullptr)
@@ -141,7 +141,7 @@ class LiveRangeEdit : private MachineRegisterInfo::Delegate {
141141

142142
~LiveRangeEdit() override { MRI.resetDelegate(this); }
143143

144-
LiveInterval &getParent() const {
144+
const LiveInterval &getParent() const {
145145
assert(Parent && "No parent LiveInterval");
146146
return *Parent;
147147
}
@@ -193,11 +193,11 @@ class LiveRangeEdit : private MachineRegisterInfo::Delegate {
193193

194194
/// Remat - Information needed to rematerialize at a specific location.
195195
struct Remat {
196-
VNInfo *ParentVNI; // parent_'s value at the remat location.
196+
const VNInfo *const ParentVNI; // parent_'s value at the remat location.
197197
MachineInstr *OrigMI = nullptr; // Instruction defining OrigVNI. It contains
198198
// the real expr for remat.
199199

200-
explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI) {}
200+
explicit Remat(const VNInfo *ParentVNI) : ParentVNI(ParentVNI) {}
201201
};
202202

203203
/// allUsesAvailableAt - Return true if all registers used by OrigMI at

‎llvm/include/llvm/CodeGen/LiveRegMatrix.h

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,8 @@ class LiveRegMatrix : public MachineFunctionPass {
104104
/// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
105105
/// When there is more than one kind of interference, the InterferenceKind
106106
/// with the highest enum value is returned.
107-
InterferenceKind checkInterference(LiveInterval &VirtReg, MCRegister PhysReg);
107+
InterferenceKind checkInterference(const LiveInterval &VirtReg,
108+
MCRegister PhysReg);
108109

109110
/// Check for interference in the segment [Start, End) that may prevent
110111
/// assignment to PhysReg. If this function returns true, there is
@@ -116,12 +117,12 @@ class LiveRegMatrix : public MachineFunctionPass {
116117
/// Assign VirtReg to PhysReg.
117118
/// This will mark VirtReg's live range as occupied in the LiveRegMatrix and
118119
/// update VirtRegMap. The live range is expected to be available in PhysReg.
119-
void assign(LiveInterval &VirtReg, MCRegister PhysReg);
120+
void assign(const LiveInterval &VirtReg, MCRegister PhysReg);
120121

121122
/// Unassign VirtReg from its PhysReg.
122123
/// Assuming that VirtReg was previously assigned to a PhysReg, this undoes
123124
/// the assignment and updates VirtRegMap accordingly.
124-
void unassign(LiveInterval &VirtReg);
125+
void unassign(const LiveInterval &VirtReg);
125126

126127
/// Returns true if the given \p PhysReg has any live intervals assigned.
127128
bool isPhysRegUsed(MCRegister PhysReg) const;
@@ -136,13 +137,14 @@ class LiveRegMatrix : public MachineFunctionPass {
136137
/// Check for regmask interference only.
137138
/// Return true if VirtReg crosses a regmask operand that clobbers PhysReg.
138139
/// If PhysReg is null, check if VirtReg crosses any regmask operands.
139-
bool checkRegMaskInterference(LiveInterval &VirtReg,
140+
bool checkRegMaskInterference(const LiveInterval &VirtReg,
140141
MCRegister PhysReg = MCRegister::NoRegister);
141142

142143
/// Check for regunit interference only.
143144
/// Return true if VirtReg overlaps a fixed assignment of one of PhysRegs's
144145
/// register units.
145-
bool checkRegUnitInterference(LiveInterval &VirtReg, MCRegister PhysReg);
146+
bool checkRegUnitInterference(const LiveInterval &VirtReg,
147+
MCRegister PhysReg);
146148

147149
/// Query a line of the assigned virtual register matrix directly.
148150
/// Use MCRegUnitIterator to enumerate all regunits in the desired PhysReg.

‎llvm/lib/CodeGen/LiveIntervalUnion.cpp

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,8 @@ using namespace llvm;
2626
#define DEBUG_TYPE "regalloc"
2727

2828
// Merge a LiveInterval's segments. Guarantee no overlaps.
29-
void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) {
29+
void LiveIntervalUnion::unify(const LiveInterval &VirtReg,
30+
const LiveRange &Range) {
3031
if (Range.empty())
3132
return;
3233
++Tag;
@@ -53,7 +54,8 @@ void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) {
5354
}
5455

5556
// Remove a live virtual register's segments from this union.
56-
void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) {
57+
void LiveIntervalUnion::extract(const LiveInterval &VirtReg,
58+
const LiveRange &Range) {
5759
if (Range.empty())
5860
return;
5961
++Tag;
@@ -99,7 +101,7 @@ void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
99101
}
100102
#endif //!NDEBUG
101103

102-
LiveInterval *LiveIntervalUnion::getOneVReg() const {
104+
const LiveInterval *LiveIntervalUnion::getOneVReg() const {
103105
if (empty())
104106
return nullptr;
105107
for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
@@ -111,7 +113,8 @@ LiveInterval *LiveIntervalUnion::getOneVReg() const {
111113

112114
// Scan the vector of interfering virtual registers in this union. Assume it's
113115
// quite small.
114-
bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
116+
bool LiveIntervalUnion::Query::isSeenInterference(
117+
const LiveInterval *VirtReg) const {
115118
return is_contained(InterferingVRegs, VirtReg);
116119
}
117120

@@ -147,14 +150,14 @@ LiveIntervalUnion::Query::collectInterferingVRegs(unsigned MaxInterferingRegs) {
147150
}
148151

149152
LiveRange::const_iterator LREnd = LR->end();
150-
LiveInterval *RecentReg = nullptr;
153+
const LiveInterval *RecentReg = nullptr;
151154
while (LiveUnionI.valid()) {
152155
assert(LRI != LREnd && "Reached end of LR");
153156

154157
// Check for overlapping interference.
155158
while (LRI->start < LiveUnionI.stop() && LRI->end > LiveUnionI.start()) {
156159
// This is an overlap, record the interfering register.
157-
LiveInterval *VReg = LiveUnionI.value();
160+
const LiveInterval *VReg = LiveUnionI.value();
158161
if (VReg != RecentReg && !isSeenInterference(VReg)) {
159162
RecentReg = VReg;
160163
InterferingVRegs.push_back(VReg);

‎llvm/lib/CodeGen/LiveIntervals.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -913,11 +913,11 @@ static bool hasLiveThroughUse(const MachineInstr *MI, Register Reg) {
913913
return false;
914914
}
915915

916-
bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
916+
bool LiveIntervals::checkRegMaskInterference(const LiveInterval &LI,
917917
BitVector &UsableRegs) {
918918
if (LI.empty())
919919
return false;
920-
LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
920+
LiveInterval::const_iterator LiveI = LI.begin(), LiveE = LI.end();
921921

922922
// Use a smaller arrays for local live ranges.
923923
ArrayRef<SlotIndex> Slots;

‎llvm/lib/CodeGen/LiveRegMatrix.cpp

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -78,13 +78,13 @@ void LiveRegMatrix::releaseMemory() {
7878

7979
template <typename Callable>
8080
static bool foreachUnit(const TargetRegisterInfo *TRI,
81-
LiveInterval &VRegInterval, MCRegister PhysReg,
81+
const LiveInterval &VRegInterval, MCRegister PhysReg,
8282
Callable Func) {
8383
if (VRegInterval.hasSubRanges()) {
8484
for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
8585
unsigned Unit = (*Units).first;
8686
LaneBitmask Mask = (*Units).second;
87-
for (LiveInterval::SubRange &S : VRegInterval.subranges()) {
87+
for (const LiveInterval::SubRange &S : VRegInterval.subranges()) {
8888
if ((S.LaneMask & Mask).any()) {
8989
if (Func(Unit, S))
9090
return true;
@@ -101,7 +101,7 @@ static bool foreachUnit(const TargetRegisterInfo *TRI,
101101
return false;
102102
}
103103

104-
void LiveRegMatrix::assign(LiveInterval &VirtReg, MCRegister PhysReg) {
104+
void LiveRegMatrix::assign(const LiveInterval &VirtReg, MCRegister PhysReg) {
105105
LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg(), TRI) << " to "
106106
<< printReg(PhysReg, TRI) << ':');
107107
assert(!VRM->hasPhys(VirtReg.reg()) && "Duplicate VirtReg assignment");
@@ -118,7 +118,7 @@ void LiveRegMatrix::assign(LiveInterval &VirtReg, MCRegister PhysReg) {
118118
LLVM_DEBUG(dbgs() << '\n');
119119
}
120120

121-
void LiveRegMatrix::unassign(LiveInterval &VirtReg) {
121+
void LiveRegMatrix::unassign(const LiveInterval &VirtReg) {
122122
Register PhysReg = VRM->getPhys(VirtReg.reg());
123123
LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg(), TRI)
124124
<< " from " << printReg(PhysReg, TRI) << ':');
@@ -143,7 +143,7 @@ bool LiveRegMatrix::isPhysRegUsed(MCRegister PhysReg) const {
143143
return false;
144144
}
145145

146-
bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg,
146+
bool LiveRegMatrix::checkRegMaskInterference(const LiveInterval &VirtReg,
147147
MCRegister PhysReg) {
148148
// Check if the cached information is valid.
149149
// The same BitVector can be reused for all PhysRegs.
@@ -161,7 +161,7 @@ bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg,
161161
return !RegMaskUsable.empty() && (!PhysReg || !RegMaskUsable.test(PhysReg));
162162
}
163163

164-
bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg,
164+
bool LiveRegMatrix::checkRegUnitInterference(const LiveInterval &VirtReg,
165165
MCRegister PhysReg) {
166166
if (VirtReg.empty())
167167
return false;
@@ -183,7 +183,8 @@ LiveIntervalUnion::Query &LiveRegMatrix::query(const LiveRange &LR,
183183
}
184184

185185
LiveRegMatrix::InterferenceKind
186-
LiveRegMatrix::checkInterference(LiveInterval &VirtReg, MCRegister PhysReg) {
186+
LiveRegMatrix::checkInterference(const LiveInterval &VirtReg,
187+
MCRegister PhysReg) {
187188
if (VirtReg.empty())
188189
return IK_Free;
189190

@@ -237,7 +238,7 @@ bool LiveRegMatrix::checkInterference(SlotIndex Start, SlotIndex End,
237238
}
238239

239240
Register LiveRegMatrix::getOneVReg(unsigned PhysReg) const {
240-
LiveInterval *VRegInterval = nullptr;
241+
const LiveInterval *VRegInterval = nullptr;
241242
for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) {
242243
if ((VRegInterval = Matrix[*Unit].getOneVReg()))
243244
return VRegInterval->reg();

0 commit comments

Comments
 (0)