Skip to content

Commit 4a0ae4f

Browse files
authored
[RISCV] Add LD_RV32/SD_RV32 to a few more functions in RISCVInstrInfo. (llvm#140640)
isLoadFromStackSlot/isStoreToStackSlot/getMemOperandsWithOffsetWidth The first 2 probably requires spills/reloads which we don't use LD_RV32/SD_RV32 for yet. I think getMemOperandsWithOffsetWidth is mainly used for load/store clustering. I think we can assume this just works.
1 parent 95e4db8 commit 4a0ae4f

File tree

1 file changed

+4
-0
lines changed

1 file changed

+4
-0
lines changed

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,7 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
156156
MemBytes = TypeSize::getFixed(4);
157157
break;
158158
case RISCV::LD:
159+
case RISCV::LD_RV32:
159160
case RISCV::FLD:
160161
MemBytes = TypeSize::getFixed(8);
161162
break;
@@ -206,6 +207,7 @@ Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
206207
MemBytes = TypeSize::getFixed(4);
207208
break;
208209
case RISCV::SD:
210+
case RISCV::SD_RV32:
209211
case RISCV::FSD:
210212
MemBytes = TypeSize::getFixed(8);
211213
break;
@@ -3057,8 +3059,10 @@ bool RISCVInstrInfo::getMemOperandsWithOffsetWidth(
30573059
case RISCV::SW_INX:
30583060
case RISCV::FSW:
30593061
case RISCV::LD:
3062+
case RISCV::LD_RV32:
30603063
case RISCV::FLD:
30613064
case RISCV::SD:
3065+
case RISCV::SD_RV32:
30623066
case RISCV::FSD:
30633067
break;
30643068
default:

0 commit comments

Comments
 (0)