Skip to content

Commit 5ab9ae1

Browse files
nitinjohnrajnitinjohnraj
committed
[RISCV] Made vrgather.vv and vrgatherei16 pseudoinstructions SEW-aware
1 parent a075ac0 commit 5ab9ae1

File tree

3 files changed

+77
-31
lines changed

3 files changed

+77
-31
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 67 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1939,6 +1939,24 @@ multiclass VPseudoBinary<VReg RetClass,
19391939
}
19401940
}
19411941

1942+
multiclass VPseudoBinary_E<VReg RetClass,
1943+
VReg Op1Class,
1944+
DAGOperand Op2Class,
1945+
LMULInfo MInfo,
1946+
int sew,
1947+
string Constraint = ""> {
1948+
let VLMul = MInfo.value in {
1949+
defvar suffix = "_" # MInfo.MX # "_E" # sew;
1950+
def suffix : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
1951+
Constraint>;
1952+
def suffix # "_TU" : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
1953+
Constraint>;
1954+
def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
1955+
Constraint>,
1956+
RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
1957+
}
1958+
}
1959+
19421960
multiclass VPseudoBinaryM<VReg RetClass,
19431961
VReg Op1Class,
19441962
DAGOperand Op2Class,
@@ -1971,6 +1989,25 @@ multiclass VPseudoBinaryEmul<VReg RetClass,
19711989
}
19721990
}
19731991

1992+
multiclass VPseudoBinaryEmul_E<VReg RetClass,
1993+
VReg Op1Class,
1994+
DAGOperand Op2Class,
1995+
LMULInfo lmul,
1996+
int sew,
1997+
LMULInfo emul,
1998+
string Constraint = ""> {
1999+
let VLMul = lmul.value in {
2000+
defvar suffix = "_" # lmul.MX # "_E" # sew # "_" # emul.MX;
2001+
def suffix : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
2002+
Constraint>;
2003+
def suffix # "_TU" : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
2004+
Constraint>;
2005+
def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
2006+
Constraint>,
2007+
RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
2008+
}
2009+
}
2010+
19742011
multiclass VPseudoTiedBinary<VReg RetClass,
19752012
DAGOperand Op2Class,
19762013
LMULInfo MInfo,
@@ -1987,6 +2024,10 @@ multiclass VPseudoBinaryV_VV<LMULInfo m, string Constraint = ""> {
19872024
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
19882025
}
19892026

2027+
multiclass VPseudoBinaryV_VV_E<LMULInfo m, int sew, string Constraint = ""> {
2028+
defm _VV : VPseudoBinary_E<m.vrclass, m.vrclass, m.vrclass, m, sew, Constraint>;
2029+
}
2030+
19902031
// Similar to VPseudoBinaryV_VV, but uses MxListF.
19912032
multiclass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = ""> {
19922033
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
@@ -1995,20 +2036,21 @@ multiclass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = ""> {
19952036
multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
19962037
foreach m = MxList in {
19972038
defvar mx = m.MX;
1998-
defvar WriteVRGatherVV_MX = !cast<SchedWrite>("WriteVRGatherVV_" # mx);
1999-
defvar ReadVRGatherVV_data_MX = !cast<SchedRead>("ReadVRGatherVV_data_" # mx);
2000-
defvar ReadVRGatherVV_index_MX = !cast<SchedRead>("ReadVRGatherVV_index_" # mx);
2001-
20022039
foreach sew = EEWList in {
20032040
defvar octuple_lmul = m.octuple;
20042041
// emul = lmul * eew / sew
20052042
defvar octuple_emul = !srl(!mul(octuple_lmul, eew), log2<sew>.val);
20062043
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
20072044
defvar emulMX = octuple_to_str<octuple_emul>.ret;
20082045
defvar emul = !cast<LMULInfo>("V_" # emulMX);
2009-
defm _VV : VPseudoBinaryEmul<m.vrclass, m.vrclass, emul.vrclass, m, emul, Constraint>,
2010-
Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_data_MX,
2011-
ReadVRGatherVV_index_MX]>;
2046+
defvar sews = SchedSEWSet<mx>.val;
2047+
foreach e = sews in {
2048+
defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
2049+
defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
2050+
defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
2051+
defm _VV : VPseudoBinaryEmul_E<m.vrclass, m.vrclass, emul.vrclass, m, e, emul, Constraint>,
2052+
Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E, ReadVRGatherVV_index_MX_E]>;
2053+
}
20122054
}
20132055
}
20142056
}
@@ -2404,23 +2446,27 @@ multiclass VPseudoBinaryM_VI<LMULInfo m> {
24042446
multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
24052447
foreach m = MxList in {
24062448
defvar mx = m.MX;
2407-
defvar WriteVRGatherVV_MX = !cast<SchedWrite>("WriteVRGatherVV_" # mx);
24082449
defvar WriteVRGatherVX_MX = !cast<SchedWrite>("WriteVRGatherVX_" # mx);
24092450
defvar WriteVRGatherVI_MX = !cast<SchedWrite>("WriteVRGatherVI_" # mx);
2410-
defvar ReadVRGatherVV_data_MX = !cast<SchedRead>("ReadVRGatherVV_data_" # mx);
2411-
defvar ReadVRGatherVV_index_MX = !cast<SchedRead>("ReadVRGatherVV_index_" # mx);
24122451
defvar ReadVRGatherVX_data_MX = !cast<SchedRead>("ReadVRGatherVX_data_" # mx);
24132452
defvar ReadVRGatherVX_index_MX = !cast<SchedRead>("ReadVRGatherVX_index_" # mx);
24142453
defvar ReadVRGatherVI_data_MX = !cast<SchedRead>("ReadVRGatherVI_data_" # mx);
24152454

2416-
defm "" : VPseudoBinaryV_VV<m, Constraint>,
2417-
Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_data_MX,
2418-
ReadVRGatherVV_index_MX, ReadVMask]>;
24192455
defm "" : VPseudoBinaryV_VX<m, Constraint>,
24202456
Sched<[WriteVRGatherVX_MX, ReadVRGatherVX_data_MX,
24212457
ReadVRGatherVX_index_MX, ReadVMask]>;
24222458
defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
24232459
Sched<[WriteVRGatherVI_MX, ReadVRGatherVI_data_MX, ReadVMask]>;
2460+
2461+
defvar sews = SchedSEWSet<mx>.val;
2462+
foreach e = sews in {
2463+
defvar WriteVRGatherVV_MX_E = !cast<SchedWrite>("WriteVRGatherVV_" # mx # "_E" # e);
2464+
defvar ReadVRGatherVV_data_MX_E = !cast<SchedRead>("ReadVRGatherVV_data_" # mx # "_E" # e);
2465+
defvar ReadVRGatherVV_index_MX_E = !cast<SchedRead>("ReadVRGatherVV_index_" # mx # "_E" # e);
2466+
defm "" : VPseudoBinaryV_VV_E<m, e, Constraint>,
2467+
Sched<[WriteVRGatherVV_MX_E, ReadVRGatherVV_data_MX_E,
2468+
ReadVRGatherVV_index_MX_E, ReadVMask]>;
2469+
}
24242470
}
24252471
}
24262472

@@ -4457,18 +4503,19 @@ multiclass VPatBinaryV_VV<string intrinsic, string instruction,
44574503
vti.RegClass, vti.RegClass>;
44584504
}
44594505

4460-
multiclass VPatBinaryV_VV_INT<string intrinsic, string instruction,
4506+
multiclass VPatBinaryV_VV_INT_E<string intrinsic, string instruction,
44614507
list<VTypeInfo> vtilist> {
44624508
foreach vti = vtilist in {
44634509
defvar ivti = GetIntVTypeInfo<vti>.Vti;
4464-
defm : VPatBinaryTA<intrinsic, instruction # "_VV_" # vti.LMul.MX,
4510+
defm : VPatBinaryTA<intrinsic,
4511+
instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,
44654512
vti.Vector, vti.Vector, ivti.Vector, vti.Mask,
44664513
vti.Log2SEW, vti.RegClass,
44674514
vti.RegClass, vti.RegClass>;
44684515
}
44694516
}
44704517

4471-
multiclass VPatBinaryV_VV_INT_EEW<string intrinsic, string instruction,
4518+
multiclass VPatBinaryV_VV_INT_E_EEW<string intrinsic, string instruction,
44724519
int eew, list<VTypeInfo> vtilist> {
44734520
foreach vti = vtilist in {
44744521
// emul = lmul * eew / sew
@@ -4478,7 +4525,7 @@ multiclass VPatBinaryV_VV_INT_EEW<string intrinsic, string instruction,
44784525
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
44794526
defvar emul_str = octuple_to_str<octuple_emul>.ret;
44804527
defvar ivti = !cast<VTypeInfo>("VI" # eew # emul_str);
4481-
defvar inst = instruction # "_VV_" # vti.LMul.MX # "_" # emul_str;
4528+
defvar inst = instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
44824529
defm : VPatBinaryTA<intrinsic, inst,
44834530
vti.Vector, vti.Vector, ivti.Vector, vti.Mask,
44844531
vti.Log2SEW, vti.RegClass,
@@ -4967,7 +5014,7 @@ multiclass VPatBinaryM_VX_VI<string intrinsic, string instruction,
49675014

49685015
multiclass VPatBinaryV_VV_VX_VI_INT<string intrinsic, string instruction,
49695016
list<VTypeInfo> vtilist, Operand ImmType = simm5>
4970-
: VPatBinaryV_VV_INT<intrinsic#"_vv", instruction, vtilist>,
5017+
: VPatBinaryV_VV_INT_E<intrinsic#"_vv", instruction, vtilist>,
49715018
VPatBinaryV_VX_INT<intrinsic#"_vx", instruction, vtilist>,
49725019
VPatBinaryV_VI<intrinsic#"_vx", instruction, vtilist, ImmType>;
49735020

@@ -6455,14 +6502,14 @@ let Predicates = [HasVInstructionsAnyF] in {
64556502
let Predicates = [HasVInstructions] in {
64566503
defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
64576504
AllIntegerVectors, uimm5>;
6458-
defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
6505+
defm : VPatBinaryV_VV_INT_E_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
64596506
/* eew */ 16, AllIntegerVectors>;
64606507
} // Predicates = [HasVInstructions]
64616508

64626509
let Predicates = [HasVInstructionsAnyF] in {
64636510
defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
64646511
AllFloatVectors, uimm5>;
6465-
defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
6512+
defm : VPatBinaryV_VV_INT_E_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
64666513
/* eew */ 16, AllFloatVectors>;
64676514
} // Predicates = [HasVInstructionsAnyF]
64686515

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2047,7 +2047,7 @@ foreach vti = AllIntegerVectors in {
20472047
vti.RegClass:$merge,
20482048
(vti.Mask V0),
20492049
VLOpFrag)),
2050-
(!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK")
2050+
(!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_E"# vti.SEW#"_MASK")
20512051
vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,
20522052
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
20532053
def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
@@ -2073,7 +2073,7 @@ foreach vti = AllIntegerVectors in {
20732073
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
20742074
defvar emul_str = octuple_to_str<octuple_emul>.ret;
20752075
defvar ivti = !cast<VTypeInfo>("VI16" # emul_str);
2076-
defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str;
2076+
defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
20772077

20782078
def : Pat<(vti.Vector
20792079
(riscv_vrgatherei16_vv_vl vti.RegClass:$rs2,
@@ -2117,7 +2117,7 @@ foreach vti = AllFloatVectors in {
21172117
vti.RegClass:$merge,
21182118
(vti.Mask V0),
21192119
VLOpFrag)),
2120-
(!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK")
2120+
(!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_E"# vti.SEW#"_MASK")
21212121
vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,
21222122
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
21232123
def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
@@ -2143,7 +2143,7 @@ foreach vti = AllFloatVectors in {
21432143
if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
21442144
defvar emul_str = octuple_to_str<octuple_emul>.ret;
21452145
defvar ivti = !cast<VTypeInfo>("VI16" # emul_str);
2146-
defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str;
2146+
defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
21472147

21482148
def : Pat<(vti.Vector
21492149
(riscv_vrgatherei16_vv_vl vti.RegClass:$rs2,

‎llvm/lib/Target/RISCV/RISCVScheduleV.td

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -383,7 +383,7 @@ defm "" : LMULSchedWrites<"WriteVISlideI">;
383383
defm "" : LMULSchedWrites<"WriteVISlide1X">;
384384
defm "" : LMULSchedWrites<"WriteVFSlide1F">;
385385
// 16.4. Vector Register Gather Instructions
386-
defm "" : LMULSchedWrites<"WriteVRGatherVV">;
386+
defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">;
387387
defm "" : LMULSchedWrites<"WriteVRGatherVX">;
388388
defm "" : LMULSchedWrites<"WriteVRGatherVI">;
389389
// 16.5. Vector Compress Instruction
@@ -605,8 +605,8 @@ defm "" : LMULSchedReads<"ReadVISlideX">;
605605
defm "" : LMULSchedReads<"ReadVFSlideV">;
606606
defm "" : LMULSchedReads<"ReadVFSlideF">;
607607
// 16.4. Vector Register Gather Instructions
608-
defm "" : LMULSchedReads<"ReadVRGatherVV_data">;
609-
defm "" : LMULSchedReads<"ReadVRGatherVV_index">;
608+
defm "" : LMULSEWSchedReads<"ReadVRGatherVV_data">;
609+
defm "" : LMULSEWSchedReads<"ReadVRGatherVV_index">;
610610
defm "" : LMULSchedReads<"ReadVRGatherVX_data">;
611611
defm "" : LMULSchedReads<"ReadVRGatherVX_index">;
612612
defm "" : LMULSchedReads<"ReadVRGatherVI_data">;
@@ -800,7 +800,7 @@ defm "" : LMULWriteRes<"WriteVISlideX", []>;
800800
defm "" : LMULWriteRes<"WriteVISlideI", []>;
801801
defm "" : LMULWriteRes<"WriteVISlide1X", []>;
802802
defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
803-
defm "" : LMULWriteRes<"WriteVRGatherVV", []>;
803+
defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>;
804804
defm "" : LMULWriteRes<"WriteVRGatherVX", []>;
805805
defm "" : LMULWriteRes<"WriteVRGatherVI", []>;
806806
defm "" : LMULSEWWriteRes<"WriteVCompressV", []>;
@@ -958,13 +958,12 @@ defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
958958
defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
959959
defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
960960
defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
961-
defm "" : LMULReadAdvance<"ReadVRGatherVV_data", 0>;
962-
defm "" : LMULReadAdvance<"ReadVRGatherVV_index", 0>;
961+
defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
962+
defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
963963
defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
964964
defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
965965
defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
966966
defm "" : LMULReadAdvance<"ReadVGatherV", 0>;
967-
defm "" : LMULReadAdvance<"ReadVGatherX", 0>;
968967
defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
969968
// These are already LMUL aware
970969
def : ReadAdvance<ReadVMov1V, 0>;

0 commit comments

Comments
 (0)