[X86] AMD Zen 3: MOVSX32rr32 is a zero-cycle move

It measures as such, and the reference docs agree.

I can't easily add a MCA test, because there's no mnemonic for it,
it can only be disassembled or created as a MCInst.

Author: LebedevRI

llvm/lib/Target/X86/X86ScheduleZnver3.td

@@ -1466,7 +1466,7 @@ def : IsOptimizableRegisterMove<[
     // GPR variants.
     MOV32rr, MOV32rr_REV,
     MOV64rr, MOV64rr_REV,
-    // FIXME: MOVSXD32rr, but it is only supported in disassembler.
+    MOVSX32rr32,
     // FIXME: XCHG32rr/XCHG64rr after MCA is fixed
 
     // MMX variants.