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Merge commit '9621bbdf62d3' from llvm.org/main into next
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‎llvm/test/CodeGen/RISCV/addimm-mulimm.ll

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@@ -338,3 +338,225 @@ define i64 @add_mul_combine_reject_d3(i64 %x) {
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%tmp1 = mul i64 %tmp0, 192
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ret i64 %tmp1
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}
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define i32 @add_mul_combine_reject_e1(i32 %x) {
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; RV32IMB-LABEL: add_mul_combine_reject_e1:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a1, zero, 29
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; RV32IMB-NEXT: mul a0, a0, a1
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; RV32IMB-NEXT: lui a1, 14
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; RV32IMB-NEXT: addi a1, a1, -185
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: add_mul_combine_reject_e1:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addi a1, zero, 29
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; RV64IMB-NEXT: mulw a0, a0, a1
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; RV64IMB-NEXT: lui a1, 14
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; RV64IMB-NEXT: addiw a1, a1, -185
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; RV64IMB-NEXT: addw a0, a0, a1
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; RV64IMB-NEXT: ret
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%tmp0 = mul i32 %x, 29
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%tmp1 = add i32 %tmp0, 57159
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ret i32 %tmp1
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}
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define signext i32 @add_mul_combine_reject_e2(i32 signext %x) {
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; RV32IMB-LABEL: add_mul_combine_reject_e2:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a1, zero, 29
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; RV32IMB-NEXT: mul a0, a0, a1
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; RV32IMB-NEXT: lui a1, 14
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; RV32IMB-NEXT: addi a1, a1, -185
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: add_mul_combine_reject_e2:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addi a1, zero, 29
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; RV64IMB-NEXT: mulw a0, a0, a1
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; RV64IMB-NEXT: lui a1, 14
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; RV64IMB-NEXT: addiw a1, a1, -185
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; RV64IMB-NEXT: addw a0, a0, a1
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; RV64IMB-NEXT: ret
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%tmp0 = mul i32 %x, 29
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%tmp1 = add i32 %tmp0, 57159
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ret i32 %tmp1
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}
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define i64 @add_mul_combine_reject_e3(i64 %x) {
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; RV32IMB-LABEL: add_mul_combine_reject_e3:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a2, zero, 29
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; RV32IMB-NEXT: mul a1, a1, a2
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; RV32IMB-NEXT: mulhu a3, a0, a2
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; RV32IMB-NEXT: add a1, a3, a1
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; RV32IMB-NEXT: mul a2, a0, a2
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; RV32IMB-NEXT: lui a0, 14
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; RV32IMB-NEXT: addi a0, a0, -185
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; RV32IMB-NEXT: add a0, a2, a0
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; RV32IMB-NEXT: sltu a2, a0, a2
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; RV32IMB-NEXT: add a1, a1, a2
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: add_mul_combine_reject_e3:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addi a1, zero, 29
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; RV64IMB-NEXT: mul a0, a0, a1
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; RV64IMB-NEXT: lui a1, 14
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; RV64IMB-NEXT: addiw a1, a1, -185
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; RV64IMB-NEXT: add a0, a0, a1
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; RV64IMB-NEXT: ret
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%tmp0 = mul i64 %x, 29
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%tmp1 = add i64 %tmp0, 57159
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ret i64 %tmp1
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}
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define i32 @add_mul_combine_reject_f1(i32 %x) {
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; RV32IMB-LABEL: add_mul_combine_reject_f1:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a1, zero, 29
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; RV32IMB-NEXT: mul a0, a0, a1
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; RV32IMB-NEXT: lui a1, 14
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; RV32IMB-NEXT: addi a1, a1, -145
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: add_mul_combine_reject_f1:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addi a1, zero, 29
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; RV64IMB-NEXT: mulw a0, a0, a1
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; RV64IMB-NEXT: lui a1, 14
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; RV64IMB-NEXT: addiw a1, a1, -145
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; RV64IMB-NEXT: addw a0, a0, a1
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; RV64IMB-NEXT: ret
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%tmp0 = mul i32 %x, 29
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%tmp1 = add i32 %tmp0, 57199
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ret i32 %tmp1
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}
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define signext i32 @add_mul_combine_reject_f2(i32 signext %x) {
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; RV32IMB-LABEL: add_mul_combine_reject_f2:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a1, zero, 29
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; RV32IMB-NEXT: mul a0, a0, a1
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; RV32IMB-NEXT: lui a1, 14
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; RV32IMB-NEXT: addi a1, a1, -145
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: add_mul_combine_reject_f2:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addi a1, zero, 29
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; RV64IMB-NEXT: mulw a0, a0, a1
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; RV64IMB-NEXT: lui a1, 14
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; RV64IMB-NEXT: addiw a1, a1, -145
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; RV64IMB-NEXT: addw a0, a0, a1
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; RV64IMB-NEXT: ret
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%tmp0 = mul i32 %x, 29
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%tmp1 = add i32 %tmp0, 57199
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ret i32 %tmp1
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}
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define i64 @add_mul_combine_reject_f3(i64 %x) {
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; RV32IMB-LABEL: add_mul_combine_reject_f3:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a2, zero, 29
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; RV32IMB-NEXT: mul a1, a1, a2
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; RV32IMB-NEXT: mulhu a3, a0, a2
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; RV32IMB-NEXT: add a1, a3, a1
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; RV32IMB-NEXT: mul a2, a0, a2
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; RV32IMB-NEXT: lui a0, 14
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; RV32IMB-NEXT: addi a0, a0, -145
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; RV32IMB-NEXT: add a0, a2, a0
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; RV32IMB-NEXT: sltu a2, a0, a2
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; RV32IMB-NEXT: add a1, a1, a2
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: add_mul_combine_reject_f3:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: addi a1, zero, 29
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; RV64IMB-NEXT: mul a0, a0, a1
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; RV64IMB-NEXT: lui a1, 14
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; RV64IMB-NEXT: addiw a1, a1, -145
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; RV64IMB-NEXT: add a0, a0, a1
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; RV64IMB-NEXT: ret
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%tmp0 = mul i64 %x, 29
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%tmp1 = add i64 %tmp0, 57199
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ret i64 %tmp1
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}
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define i32 @add_mul_combine_reject_g1(i32 %x) {
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; RV32IMB-LABEL: add_mul_combine_reject_g1:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: sh3add a1, a0, a0
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; RV32IMB-NEXT: sh3add a0, a1, a0
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; RV32IMB-NEXT: lui a1, 2
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; RV32IMB-NEXT: addi a1, a1, -882
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: add_mul_combine_reject_g1:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: sh3add a1, a0, a0
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; RV64IMB-NEXT: sh3add a0, a1, a0
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; RV64IMB-NEXT: lui a1, 2
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; RV64IMB-NEXT: addiw a1, a1, -882
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; RV64IMB-NEXT: addw a0, a0, a1
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; RV64IMB-NEXT: ret
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%tmp0 = mul i32 %x, 73
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%tmp1 = add i32 %tmp0, 7310
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ret i32 %tmp1
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}
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define signext i32 @add_mul_combine_reject_g2(i32 signext %x) {
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; RV32IMB-LABEL: add_mul_combine_reject_g2:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: sh3add a1, a0, a0
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; RV32IMB-NEXT: sh3add a0, a1, a0
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; RV32IMB-NEXT: lui a1, 2
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; RV32IMB-NEXT: addi a1, a1, -882
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; RV32IMB-NEXT: add a0, a0, a1
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: add_mul_combine_reject_g2:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: sh3add a1, a0, a0
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; RV64IMB-NEXT: sh3add a0, a1, a0
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; RV64IMB-NEXT: lui a1, 2
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; RV64IMB-NEXT: addiw a1, a1, -882
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; RV64IMB-NEXT: addw a0, a0, a1
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; RV64IMB-NEXT: ret
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%tmp0 = mul i32 %x, 73
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%tmp1 = add i32 %tmp0, 7310
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ret i32 %tmp1
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}
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define i64 @add_mul_combine_reject_g3(i64 %x) {
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; RV32IMB-LABEL: add_mul_combine_reject_g3:
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; RV32IMB: # %bb.0:
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; RV32IMB-NEXT: addi a2, zero, 73
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; RV32IMB-NEXT: mul a1, a1, a2
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; RV32IMB-NEXT: mulhu a3, a0, a2
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; RV32IMB-NEXT: add a1, a3, a1
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; RV32IMB-NEXT: mul a2, a0, a2
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; RV32IMB-NEXT: lui a0, 2
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; RV32IMB-NEXT: addi a0, a0, -882
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; RV32IMB-NEXT: add a0, a2, a0
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; RV32IMB-NEXT: sltu a2, a0, a2
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; RV32IMB-NEXT: add a1, a1, a2
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; RV32IMB-NEXT: ret
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;
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; RV64IMB-LABEL: add_mul_combine_reject_g3:
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; RV64IMB: # %bb.0:
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; RV64IMB-NEXT: sh3add a1, a0, a0
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; RV64IMB-NEXT: sh3add a0, a1, a0
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; RV64IMB-NEXT: lui a1, 2
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; RV64IMB-NEXT: addiw a1, a1, -882
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; RV64IMB-NEXT: add a0, a0, a1
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; RV64IMB-NEXT: ret
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%tmp0 = mul i64 %x, 73
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%tmp1 = add i64 %tmp0, 7310
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ret i64 %tmp1
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}

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