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1 parent b8b5e87 commit 9d792feCopy full SHA for 9d792fe
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2009,7 +2009,7 @@ bool RISCVTargetLowering::isDesirableToCommuteWithShift(
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auto *C1 = dyn_cast<ConstantSDNode>(N0->getOperand(1));
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auto *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1));
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if (C1 && C2) {
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- APInt C1Int = C1->getAPIntValue();
+ const APInt &C1Int = C1->getAPIntValue();
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APInt ShiftedC1Int = C1Int << C2->getAPIntValue();
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// We can materialise `c1 << c2` into an add immediate, so it's "free",
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