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LebedevRILebedevRI
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Revert rest of IRBuilderBase's short-circuiting folds
Upon further investigation and discussion, this is actually the opposite direction from what we should be taking, and this direction wouldn't solve the motivational problem anyway. Additionally, some more (polly) tests have escaped being updated. So, let's just take a step back here. This reverts commit f3190de. This reverts commit 749581d. This reverts commit f3df87d. This reverts commit ab1dbce.
1 parent a0c1e75 commit b291597

30 files changed

+733
-676
lines changed

‎clang/test/CodeGen/arm-mve-intrinsics/vadc.c

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
// CHECK-NEXT: [[TMP0:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0)
1010
// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 1
1111
// CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 29
12-
// CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
12+
// CHECK-NEXT: [[TMP3:%.*]] = and i32 1, [[TMP2]]
1313
// CHECK-NEXT: store i32 [[TMP3]], i32* [[CARRY_OUT:%.*]], align 4
1414
// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 0
1515
// CHECK-NEXT: ret <4 x i32> [[TMP4]]
@@ -30,7 +30,7 @@ int32x4_t test_vadciq_s32(int32x4_t a, int32x4_t b, unsigned *carry_out)
3030
// CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]])
3131
// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1
3232
// CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29
33-
// CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 1
33+
// CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]
3434
// CHECK-NEXT: store i32 [[TMP5]], i32* [[CARRY]], align 4
3535
// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0
3636
// CHECK-NEXT: ret <4 x i32> [[TMP6]]
@@ -51,7 +51,7 @@ uint32x4_t test_vadcq_u32(uint32x4_t a, uint32x4_t b, unsigned *carry)
5151
// CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, <4 x i1> [[TMP1]])
5252
// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1
5353
// CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29
54-
// CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 1
54+
// CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]
5555
// CHECK-NEXT: store i32 [[TMP5]], i32* [[CARRY_OUT:%.*]], align 4
5656
// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0
5757
// CHECK-NEXT: ret <4 x i32> [[TMP6]]
@@ -74,7 +74,7 @@ uint32x4_t test_vadciq_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, un
7474
// CHECK-NEXT: [[TMP4:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]], <4 x i1> [[TMP3]])
7575
// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 1
7676
// CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP5]], 29
77-
// CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 1
77+
// CHECK-NEXT: [[TMP7:%.*]] = and i32 1, [[TMP6]]
7878
// CHECK-NEXT: store i32 [[TMP7]], i32* [[CARRY]], align 4
7979
// CHECK-NEXT: [[TMP8:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 0
8080
// CHECK-NEXT: ret <4 x i32> [[TMP8]]
@@ -93,7 +93,7 @@ int32x4_t test_vadcq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigne
9393
// CHECK-NEXT: [[TMP0:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0)
9494
// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 1
9595
// CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 29
96-
// CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
96+
// CHECK-NEXT: [[TMP3:%.*]] = and i32 1, [[TMP2]]
9797
// CHECK-NEXT: store i32 [[TMP3]], i32* [[CARRY_OUT:%.*]], align 4
9898
// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 0
9999
// CHECK-NEXT: ret <4 x i32> [[TMP4]]
@@ -111,7 +111,7 @@ int32x4_t test_vsbciq_s32(int32x4_t a, int32x4_t b, unsigned *carry_out) {
111111
// CHECK-NEXT: [[TMP0:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0)
112112
// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 1
113113
// CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 29
114-
// CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
114+
// CHECK-NEXT: [[TMP3:%.*]] = and i32 1, [[TMP2]]
115115
// CHECK-NEXT: store i32 [[TMP3]], i32* [[CARRY_OUT:%.*]], align 4
116116
// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 0
117117
// CHECK-NEXT: ret <4 x i32> [[TMP4]]
@@ -131,7 +131,7 @@ uint32x4_t test_vsbciq_u32(uint32x4_t a, uint32x4_t b, unsigned *carry_out) {
131131
// CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]])
132132
// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1
133133
// CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29
134-
// CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 1
134+
// CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]
135135
// CHECK-NEXT: store i32 [[TMP5]], i32* [[CARRY]], align 4
136136
// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0
137137
// CHECK-NEXT: ret <4 x i32> [[TMP6]]
@@ -151,7 +151,7 @@ int32x4_t test_vsbcq_s32(int32x4_t a, int32x4_t b, unsigned *carry) {
151151
// CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]])
152152
// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1
153153
// CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29
154-
// CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 1
154+
// CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]
155155
// CHECK-NEXT: store i32 [[TMP5]], i32* [[CARRY]], align 4
156156
// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0
157157
// CHECK-NEXT: ret <4 x i32> [[TMP6]]
@@ -171,7 +171,7 @@ uint32x4_t test_vsbcq_u32(uint32x4_t a, uint32x4_t b, unsigned *carry) {
171171
// CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, <4 x i1> [[TMP1]])
172172
// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1
173173
// CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29
174-
// CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 1
174+
// CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]
175175
// CHECK-NEXT: store i32 [[TMP5]], i32* [[CARRY_OUT:%.*]], align 4
176176
// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0
177177
// CHECK-NEXT: ret <4 x i32> [[TMP6]]
@@ -191,7 +191,7 @@ int32x4_t test_vsbciq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, unsign
191191
// CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, <4 x i1> [[TMP1]])
192192
// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1
193193
// CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29
194-
// CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 1
194+
// CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]
195195
// CHECK-NEXT: store i32 [[TMP5]], i32* [[CARRY_OUT:%.*]], align 4
196196
// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0
197197
// CHECK-NEXT: ret <4 x i32> [[TMP6]]
@@ -213,7 +213,7 @@ uint32x4_t test_vsbciq_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, un
213213
// CHECK-NEXT: [[TMP4:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]], <4 x i1> [[TMP3]])
214214
// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 1
215215
// CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP5]], 29
216-
// CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 1
216+
// CHECK-NEXT: [[TMP7:%.*]] = and i32 1, [[TMP6]]
217217
// CHECK-NEXT: store i32 [[TMP7]], i32* [[CARRY]], align 4
218218
// CHECK-NEXT: [[TMP8:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 0
219219
// CHECK-NEXT: ret <4 x i32> [[TMP8]]
@@ -235,7 +235,7 @@ int32x4_t test_vsbcq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigne
235235
// CHECK-NEXT: [[TMP4:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]], <4 x i1> [[TMP3]])
236236
// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 1
237237
// CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP5]], 29
238-
// CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 1
238+
// CHECK-NEXT: [[TMP7:%.*]] = and i32 1, [[TMP6]]
239239
// CHECK-NEXT: store i32 [[TMP7]], i32* [[CARRY]], align 4
240240
// CHECK-NEXT: [[TMP8:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 0
241241
// CHECK-NEXT: ret <4 x i32> [[TMP8]]

‎clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -172,13 +172,13 @@ char *nullptr_var(unsigned long offset) {
172172
// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET:.*]] = extractvalue { i64, i1 } %[[COMPUTED_OFFSET_AGGREGATE]], 0, !nosanitize
173173
// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP:.*]] = add i64 0, %[[COMPUTED_OFFSET]], !nosanitize
174174
// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP_IS_NOT_NULL:.*]] = icmp ne i64 %[[COMPUTED_GEP]], 0, !nosanitize
175+
// CHECK-SANITIZE-C-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = and i1 false, %[[COMPUTED_GEP_IS_NOT_NULL]], !nosanitize
175176
// CHECK-SANITIZE-CPP-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = icmp eq i1 false, %[[COMPUTED_GEP_IS_NOT_NULL]], !nosanitize
176177
// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_DID_NOT_OVERFLOW:.*]] = xor i1 %[[COMPUTED_OFFSET_OVERFLOWED]], true, !nosanitize
177178
// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP_IS_UGE_BASE:.*]] = icmp uge i64 %[[COMPUTED_GEP]], 0, !nosanitize
178179
// CHECK-SANITIZE-NEXT: %[[GEP_DID_NOT_OVERFLOW:.*]] = and i1 %[[COMPUTED_GEP_IS_UGE_BASE]], %[[COMPUTED_OFFSET_DID_NOT_OVERFLOW]], !nosanitize
179-
// CHECK-SANITIZE-CPP-NEXT: %[[GEP_IS_OKAY:.*]] = and i1 %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL]], %[[GEP_DID_NOT_OVERFLOW]], !nosanitize
180-
// CHECK-SANITIZE-C-NEXT: br i1 false, label %[[CONT:.*]], label %[[HANDLER_POINTER_OVERFLOW:[^,]+]],{{.*}} !nosanitize
181-
// CHECK-SANITIZE-CPP-NEXT: br i1 %[[GEP_IS_OKAY]], label %[[CONT:.*]], label %[[HANDLER_POINTER_OVERFLOW:[^,]+]],{{.*}} !nosanitize
180+
// CHECK-SANITIZE-NEXT: %[[GEP_IS_OKAY:.*]] = and i1 %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL]], %[[GEP_DID_NOT_OVERFLOW]], !nosanitize
181+
// CHECK-SANITIZE-NEXT: br i1 %[[GEP_IS_OKAY]], label %[[CONT:.*]], label %[[HANDLER_POINTER_OVERFLOW:[^,]+]],{{.*}} !nosanitize
182182
// CHECK-SANITIZE: [[HANDLER_POINTER_OVERFLOW]]:
183183
// CHECK-SANITIZE-NORECOVER-NEXT: call void @__ubsan_handle_pointer_overflow_abort(i8* bitcast ({ {{{.*}}} }* @[[LINE_500]] to i8*), i64 0, i64 %[[COMPUTED_GEP]])
184184
// CHECK-SANITIZE-RECOVER-NEXT: call void @__ubsan_handle_pointer_overflow(i8* bitcast ({ {{{.*}}} }* @[[LINE_500]] to i8*), i64 0, i64 %[[COMPUTED_GEP]])
@@ -258,7 +258,7 @@ char *one_var(unsigned long offset) {
258258
// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET:.*]] = extractvalue { i64, i1 } %[[COMPUTED_OFFSET_AGGREGATE]], 0, !nosanitize
259259
// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP:.*]] = add i64 1, %[[COMPUTED_OFFSET]], !nosanitize
260260
// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP_IS_NOT_NULL:.*]] = icmp ne i64 %[[COMPUTED_GEP]], 0, !nosanitize
261-
// CHECK-SANITIZE-C-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = and i1 %[[COMPUTED_GEP_IS_NOT_NULL]], icmp ne (i8* inttoptr (i64 1 to i8*), i8* null), !nosanitize
261+
// CHECK-SANITIZE-C-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = and i1 icmp ne (i8* inttoptr (i64 1 to i8*), i8* null), %[[COMPUTED_GEP_IS_NOT_NULL]], !nosanitize
262262
// CHECK-SANITIZE-CPP-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = icmp eq i1 icmp ne (i8* inttoptr (i64 1 to i8*), i8* null), %[[COMPUTED_GEP_IS_NOT_NULL]], !nosanitize
263263
// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_DID_NOT_OVERFLOW:.*]] = xor i1 %[[COMPUTED_OFFSET_OVERFLOWED]], true, !nosanitize
264264
// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP_IS_UGE_BASE:.*]] = icmp uge i64 %[[COMPUTED_GEP]], 1, !nosanitize
@@ -344,7 +344,7 @@ char *allones_var(unsigned long offset) {
344344
// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET:.*]] = extractvalue { i64, i1 } %[[COMPUTED_OFFSET_AGGREGATE]], 0, !nosanitize
345345
// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP:.*]] = add i64 -1, %[[COMPUTED_OFFSET]], !nosanitize
346346
// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP_IS_NOT_NULL:.*]] = icmp ne i64 %[[COMPUTED_GEP]], 0, !nosanitize
347-
// CHECK-SANITIZE-C-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = and i1 %[[COMPUTED_GEP_IS_NOT_NULL]], icmp ne (i8* inttoptr (i64 -1 to i8*), i8* null), !nosanitize
347+
// CHECK-SANITIZE-C-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = and i1 icmp ne (i8* inttoptr (i64 -1 to i8*), i8* null), %[[COMPUTED_GEP_IS_NOT_NULL]], !nosanitize
348348
// CHECK-SANITIZE-CPP-NEXT: %[[BOTH_POINTERS_ARE_NULL_OR_BOTH_ARE_NONNULL:.*]] = icmp eq i1 icmp ne (i8* inttoptr (i64 -1 to i8*), i8* null), %[[COMPUTED_GEP_IS_NOT_NULL]], !nosanitize
349349
// CHECK-SANITIZE-NEXT: %[[COMPUTED_OFFSET_DID_NOT_OVERFLOW:.*]] = xor i1 %[[COMPUTED_OFFSET_OVERFLOWED]], true, !nosanitize
350350
// CHECK-SANITIZE-NEXT: %[[COMPUTED_GEP_IS_UGE_BASE:.*]] = icmp uge i64 %[[COMPUTED_GEP]], -1, !nosanitize

‎clang/test/CodeGen/ubsan-pointer-overflow.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,7 @@ void struct_index(struct S1 *p) {
8585
// CHECK: getelementptr inbounds %struct.S1, %struct.S1* [[P:%.*]], i64 10
8686
// CHECK-NEXT: [[BASE:%.*]] = ptrtoint %struct.S1* [[P]] to i64, !nosanitize
8787
// CHECK-NEXT: [[COMPGEP:%.*]] = add i64 [[BASE]], 240, !nosanitize
88+
// CHECK: select
8889
// CHECK: @__ubsan_handle_pointer_overflow{{.*}} i64 [[BASE]], i64 [[COMPGEP]]) {{.*}}, !nosanitize
8990

9091
// CHECK-NOT: @__ubsan_handle_pointer_overflow

‎clang/test/CodeGenCXX/cfi-mfcall.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,8 +25,9 @@ void f(S *s, void (S::*p)()) {
2525

2626
// CHECK: [[NVFPTR:%.*]] = bitcast void (%struct.S*)* {{.*}} to i8*
2727
// CHECK: [[TT1:%.*]] = call i1 @llvm.type.test(i8* [[NVFPTR]], metadata !"_ZTSM2B1FvvE")
28+
// CHECK: [[OR1:%.*]] = or i1 false, [[TT1]]
2829
// CHECK: [[TT2:%.*]] = call i1 @llvm.type.test(i8* [[NVFPTR]], metadata !"_ZTSM2B2FvvE")
29-
// CHECK: [[OR2:%.*]] = or i1 [[TT1]], [[TT2]]
30+
// CHECK: [[OR2:%.*]] = or i1 [[OR1]], [[TT2]]
3031
// CHECK: br i1 [[OR2]], label {{.*}}, label %[[TRAP2:[^,]*]]
3132

3233
// CHECK: [[TRAP2]]:

‎clang/test/CodeGenCXX/ext-vector-type-conditional.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,7 @@ void OneScalarOp() {
198198
// CHECK: [[NEG:%.+]] = icmp slt <4 x i32> [[COND]], zeroinitializer
199199
// CHECK: [[SEXT:%.+]] = sext <4 x i1> [[NEG]] to <4 x i32>
200200
// CHECK: [[XOR:%.+]] = xor <4 x i32> [[SEXT]], <i32 -1, i32 -1, i32 -1, i32 -1>
201-
// CHECK: [[RHS_AND:%.+]] = and <4 x i32> [[XOR]], <i32 5, i32 5, i32 5, i32 5>
201+
// CHECK: [[RHS_AND:%.+]] = and <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[XOR]]
202202
// CHECK: [[LHS_AND:%.+]] = and <4 x i32> [[LHS]], [[SEXT]]
203203
// CHECK: = or <4 x i32> [[RHS_AND]], [[LHS_AND]]
204204

@@ -224,7 +224,7 @@ void OneScalarOp() {
224224
// CHECK: [[SEXT:%.+]] = sext <4 x i1> [[NEG]] to <4 x i64>
225225
// CHECK: [[XOR:%.+]] = xor <4 x i64> [[SEXT]], <i64 -1, i64 -1, i64 -1, i64 -1>
226226
// CHECK: [[LHS_CAST:%.+]] = bitcast <4 x double> [[LHS]] to <4 x i64>
227-
// CHECK: [[RHS_AND:%.+]] = and <4 x i64> [[XOR]], <i64 4618441417868443648, i64 4618441417868443648, i64 4618441417868443648, i64 4618441417868443648>
227+
// CHECK: [[RHS_AND:%.+]] = and <4 x i64> <i64 4618441417868443648, i64 4618441417868443648, i64 4618441417868443648, i64 4618441417868443648>, [[XOR]]
228228
// CHECK: [[LHS_AND:%.+]] = and <4 x i64> [[LHS_CAST]], [[SEXT]]
229229
// CHECK: = or <4 x i64> [[RHS_AND]], [[LHS_AND]]
230230

@@ -234,7 +234,7 @@ void OneScalarOp() {
234234
// CHECK: [[NEG:%.+]] = icmp slt <4 x i64> [[COND]], zeroinitializer
235235
// CHECK: [[SEXT:%.+]] = sext <4 x i1> [[NEG]] to <4 x i64>
236236
// CHECK: [[XOR:%.+]] = xor <4 x i64> [[SEXT]], <i64 -1, i64 -1, i64 -1, i64 -1>
237-
// CHECK: [[RHS_AND:%.+]] = and <4 x i64> [[XOR]], <i64 6, i64 6, i64 6, i64 6>
237+
// CHECK: [[RHS_AND:%.+]] = and <4 x i64> <i64 6, i64 6, i64 6, i64 6>, [[XOR]]
238238
// CHECK: [[LHS_AND:%.+]] = and <4 x i64> [[LHS]], [[SEXT]]
239239
// CHECK: [[OR:%.+]] = or <4 x i64> [[RHS_AND]], [[LHS_AND]]
240240

‎clang/test/CodeGenCXX/pr27030.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,5 +11,6 @@ void test1() { (int A::*)(a); }
1111
// CHECK: br i1 %[[memptr_cmp]]
1212

1313
// CHECK: %[[adj:.*]] = sub nsw i32 %[[load]], 0
14+
// CHECK: %[[nv_adj:.*]] = select i1 true, i32 %[[adj]], i32 0
1415

15-
// CHECK: %[[memptr_converted:.*]] = phi i32 [ -1, {{.*}} ], [ %[[adj]], {{.*}} ]
16+
// CHECK: %[[memptr_converted:.*]] = phi i32 [ -1, {{.*}} ], [ %[[nv_adj]], {{.*}} ]

‎clang/test/CodeGenObjC/ubsan-nullability.m

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -102,8 +102,9 @@ void nonnull_init2(int *p) {
102102
int *arg4,
103103
int arg5, ...) {
104104
// CHECK: [[ARG1CMP:%.*]] = icmp ne i32* %arg1, null, !nosanitize
105+
// CHECK-NEXT: [[DO_RV_CHECK_1:%.*]] = and i1 true, [[ARG1CMP]], !nosanitize
105106
// CHECK: [[ARG2CMP:%.*]] = icmp ne i32* %arg2, null, !nosanitize
106-
// CHECK-NEXT: [[DO_RV_CHECK_2:%.*]] = and i1 [[ARG1CMP]], [[ARG2CMP]]
107+
// CHECK-NEXT: [[DO_RV_CHECK_2:%.*]] = and i1 [[DO_RV_CHECK_1]], [[ARG2CMP]]
107108
// CHECK: [[SLOC_PTR:%.*]] = load i8*, i8** %return.sloc.ptr
108109
// CHECK-NEXT: [[SLOC_NONNULL:%.*]] = icmp ne i8* [[SLOC_PTR]], null
109110
// CHECK-NEXT: [[DO_RV_CHECK_3:%.*]] = and i1 [[SLOC_NONNULL]], [[DO_RV_CHECK_2]]
@@ -127,9 +128,10 @@ @implementation A
127128
// CHECK-LABEL: define internal i32* @"\01+[A objc_clsmethod:]"
128129
+(int *_Nonnull) objc_clsmethod: (int *_Nonnull) arg1 {
129130
// CHECK: [[ARG1CMP:%.*]] = icmp ne i32* %arg1, null, !nosanitize
131+
// CHECK-NEXT: [[DO_RV_CHECK:%.*]] = and i1 true, [[ARG1CMP]]
130132
// CHECK: [[SLOC_PTR:%.*]] = load i8*, i8** %return.sloc.ptr
131133
// CHECK-NEXT: [[SLOC_NONNULL:%.*]] = icmp ne i8* [[SLOC_PTR]], null
132-
// CHECK-NEXT: [[DO_RV_CHECK_2:%.*]] = and i1 [[SLOC_NONNULL]], [[ARG1CMP]]
134+
// CHECK-NEXT: [[DO_RV_CHECK_2:%.*]] = and i1 [[SLOC_NONNULL]], [[DO_RV_CHECK]]
133135
// CHECK: br i1 [[DO_RV_CHECK_2]], label %[[NULL:.*]], label %[[NONULL:.*]], !nosanitize
134136
// CHECK: [[NULL]]:
135137
// CHECK-NEXT: [[ICMP:%.*]] = icmp ne i32* {{.*}}, null, !nosanitize
@@ -143,9 +145,10 @@ +(int *_Nonnull) objc_clsmethod: (int *_Nonnull) arg1 {
143145
// CHECK-LABEL: define internal i32* @"\01-[A objc_method:]"
144146
-(int *_Nonnull) objc_method: (int *_Nonnull) arg1 {
145147
// CHECK: [[ARG1CMP:%.*]] = icmp ne i32* %arg1, null, !nosanitize
148+
// CHECK-NEXT: [[DO_RV_CHECK:%.*]] = and i1 true, [[ARG1CMP]]
146149
// CHECK: [[SLOC_PTR:%.*]] = load i8*, i8** %return.sloc.ptr
147150
// CHECK-NEXT: [[SLOC_NONNULL:%.*]] = icmp ne i8* [[SLOC_PTR]], null
148-
// CHECK-NEXT: [[DO_RV_CHECK_2:%.*]] = and i1 [[SLOC_NONNULL]], [[ARG1CMP]]
151+
// CHECK-NEXT: [[DO_RV_CHECK_2:%.*]] = and i1 [[SLOC_NONNULL]], [[DO_RV_CHECK]]
149152
// CHECK: br i1 [[DO_RV_CHECK_2]], label %[[NULL:.*]], label %[[NONULL:.*]], !nosanitize
150153
// CHECK: [[NULL]]:
151154
// CHECK-NEXT: [[ICMP:%.*]] = icmp ne i32* {{.*}}, null, !nosanitize

‎llvm/include/llvm/IR/IRBuilder.h

Lines changed: 2 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1360,15 +1360,9 @@ class IRBuilderBase {
13601360
}
13611361

13621362
Value *CreateAnd(Value *LHS, Value *RHS, const Twine &Name = "") {
1363-
if (!isa<Constant>(RHS) && isa<Constant>(LHS))
1364-
std::swap(LHS, RHS);
1365-
if (auto RCI = dyn_cast<ConstantInt>(RHS)) {
1366-
if (RCI->isZero())
1367-
return RHS; // LHS & 0 -> 0
1368-
if (RCI->isMinusOne())
1369-
return LHS; // LHS & -1 -> LHS
1370-
}
13711363
if (auto *RC = dyn_cast<Constant>(RHS)) {
1364+
if (isa<ConstantInt>(RC) && cast<ConstantInt>(RC)->isMinusOne())
1365+
return LHS; // LHS & -1 -> LHS
13721366
if (auto *LC = dyn_cast<Constant>(LHS))
13731367
return Insert(Folder.CreateAnd(LC, RC), Name);
13741368
}
@@ -1392,8 +1386,6 @@ class IRBuilderBase {
13921386
}
13931387

13941388
Value *CreateOr(Value *LHS, Value *RHS, const Twine &Name = "") {
1395-
if (!isa<Constant>(RHS) && isa<Constant>(LHS))
1396-
std::swap(LHS, RHS);
13971389
if (auto *RC = dyn_cast<Constant>(RHS)) {
13981390
if (RC->isNullValue())
13991391
return LHS; // LHS | 0 -> LHS

‎llvm/lib/IR/IRBuilder.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -973,14 +973,10 @@ CallInst *IRBuilderBase::CreateConstrainedFPCall(
973973

974974
Value *IRBuilderBase::CreateSelect(Value *C, Value *True, Value *False,
975975
const Twine &Name, Instruction *MDFrom) {
976-
if (auto *CC = dyn_cast<ConstantInt>(C))
977-
return CC->isOne() ? True : False;
978-
979-
if (auto *CC = dyn_cast<Constant>(C)) {
976+
if (auto *CC = dyn_cast<Constant>(C))
980977
if (auto *TC = dyn_cast<Constant>(True))
981978
if (auto *FC = dyn_cast<Constant>(False))
982979
return Insert(Folder.CreateSelect(CC, TC, FC), Name);
983-
}
984980

985981
SelectInst *Sel = SelectInst::Create(C, True, False);
986982
if (MDFrom) {

‎llvm/test/CodeGen/X86/block-placement.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -360,6 +360,7 @@ define void @unnatural_cfg2(i32* %p0, i32 %a0) {
360360
; CHECK: %loop.body2
361361
; CHECK: %loop.body4
362362
; CHECK: %loop.inner2.begin
363+
; CHECK: %loop.inner2.begin
363364
; CHECK: %loop.body3
364365
; CHECK: %loop.inner1.begin
365366
; CHECK: %bail

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