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davemgreendavemgreen
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[ARM/AArch64] Move REQUIRES after update_cc_test_checks line. NFC
c17d9b4 added REQUIRES lines to a lot of Arm and AArch64 test, but added them to the very beginning, before the existing update_cc_test_checks lines. This just moves them later so as to not mess up the existing ordering when the checks are regenerated.
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‎clang/test/CodeGen/aarch64-bf16-dotprod-intrinsics.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
42
// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \
53
// RUN: -disable-O0-optnone -emit-llvm -fno-legacy-pass-manager %s -o - | opt -S -mem2reg | FileCheck %s
64

5+
// REQUIRES: aarch64-registered-target || arm-registered-target
6+
77
#include <arm_neon.h>
88

99
// CHECK-LABEL: @test_vbfdot_f32(

‎clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
42
// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \
53
// RUN: -disable-O0-optnone -emit-llvm -fno-legacy-pass-manager %s -o - | opt -S -mem2reg | FileCheck %s
64

5+
// REQUIRES: aarch64-registered-target || arm-registered-target
6+
77
#include <arm_neon.h>
88

99
// CHECK-LABEL: @test_vcreate_bf16(

‎clang/test/CodeGen/aarch64-bf16-lane-intrinsics.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
42
// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \
53
// RUN: -disable-O0-optnone -emit-llvm -fno-legacy-pass-manager %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-LE %s
64
// RUN: %clang_cc1 -triple aarch64_be-arm-none-eabi -target-feature +neon -target-feature +bf16 \
75
// RUN: -disable-O0-optnone -emit-llvm %s -fno-legacy-pass-manager -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-BE %s
86

7+
// REQUIRES: aarch64-registered-target || arm-registered-target
8+
99
#include <arm_neon.h>
1010

1111
// CHECK-LE-LABEL: @test_vcopy_lane_bf16_v1(

‎clang/test/CodeGen/aarch64-fix-cortex-a53-835769.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
// REQUIRES: aarch64-registered-target
2-
31
// RUN: %clang -O3 -target aarch64-linux-eabi %s -S -o- \
42
// RUN: | FileCheck --check-prefix=CHECK-NO --check-prefix=CHECK %s
53
// RUN: %clang -O3 -target aarch64-linux-eabi -mfix-cortex-a53-835769 %s -S -o- 2>&1 \
@@ -14,6 +12,8 @@
1412
// RUN: %clang -O3 -target aarch64-android-eabi -mno-fix-cortex-a53-835769 %s -S -o- \
1513
// RUN: | FileCheck --check-prefix=CHECK-NO --check-prefix=CHECK %s
1614

15+
// REQUIRES: aarch64-registered-target
16+
1717
typedef long int64_t;
1818

1919
int64_t f_load_madd_64(int64_t a, int64_t b, int64_t *c) {

‎clang/test/CodeGen/aarch64-neon-2velem.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,7 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
42
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
53

6-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target || arm-registered-target
75

86
#include <arm_neon.h>
97

‎clang/test/CodeGen/aarch64-neon-3v.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,6 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
42

5-
// Test new aarch64 intrinsics and types
3+
// REQUIRES: aarch64-registered-target || arm-registered-target
64

75
#include <arm_neon.h>
86

‎clang/test/CodeGen/aarch64-neon-across.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,7 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
53

6-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target || arm-registered-target
75

86
#include <arm_neon.h>
97

‎clang/test/CodeGen/aarch64-neon-extract.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,7 @@
1-
// REQUIRES: aarch64-registered-target
21
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
32
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
43

5-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target
65

76
#include <arm_neon.h>
87

‎clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,7 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
53

6-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target || arm-registered-target
75

86
#include <arm_neon.h>
97

‎clang/test/CodeGen/aarch64-neon-fma.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,6 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
42

5-
// Test new aarch64 intrinsics and types
3+
// REQUIRES: aarch64-registered-target || arm-registered-target
64

75
#include <arm_neon.h>
86

‎clang/test/CodeGen/aarch64-neon-intrinsics.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,10 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -fallow-half-arguments-and-returns -S -disable-O0-optnone \
53
// RUN: -flax-vector-conversions=none -emit-llvm -o - %s \
64
// RUN: | opt -S -mem2reg \
75
// RUN: | FileCheck %s
86

9-
// Test new aarch64 intrinsics and types
7+
// REQUIRES: aarch64-registered-target || arm-registered-target
108

119
#include <arm_neon.h>
1210

‎clang/test/CodeGen/aarch64-neon-ldst-one.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm -o - %s \
53
// RUN: | opt -S -mem2reg | FileCheck %s
64

5+
// REQUIRES: aarch64-registered-target || arm-registered-target
6+
77
#include <arm_neon.h>
88

99
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vld1q_dup_u8(i8* %a) #0 {

‎clang/test/CodeGen/aarch64-neon-misc.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,8 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm -o - %s \
53
// RUN: | opt -S -mem2reg | FileCheck %s
64

7-
// Test new aarch64 intrinsics and types
5+
// REQUIRES: aarch64-registered-target || arm-registered-target
86

97
#include <arm_neon.h>
108

‎clang/test/CodeGen/aarch64-neon-perm.c

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,8 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
53

6-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target || arm-registered-target
5+
76
#include <arm_neon.h>
87

98
// CHECK-LABEL: @test_vuzp1_s8(

‎clang/test/CodeGen/aarch64-neon-range-checks.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -target-feature +sha3 -target-feature +sm4 -verify %s
42

3+
// REQUIRES: aarch64-registered-target || arm-registered-target
4+
55
#include <arm_neon.h>
66

77
void test_range_check_vsm3tt1a(uint32x4_t a, uint32x4_t b, uint32x4_t c) {

‎clang/test/CodeGen/aarch64-neon-scalar-copy.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
53

4+
// REQUIRES: aarch64-registered-target || arm-registered-target
5+
66
#include <arm_neon.h>
77

88
// CHECK-LABEL: define{{.*}} float @test_vdups_lane_f32(<2 x float> %a) #0 {

‎clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,7 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone \
42
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
53

6-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target || arm-registered-target
75

86
#include <arm_neon.h>
97

‎clang/test/CodeGen/aarch64-neon-sha3.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
42
// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
53
// RUN: -target-feature +sha3 -S -emit-llvm -o - %s \
64
// RUN: | FileCheck %s
75

6+
// REQUIRES: aarch64-registered-target || arm-registered-target
7+
88
#include <arm_neon.h>
99

1010
// CHECK-LABEL: @test_vsha512h(

‎clang/test/CodeGen/aarch64-neon-shifts.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -disable-O0-optnone -ffp-contract=fast -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
53

4+
// REQUIRES: aarch64-registered-target || arm-registered-target
5+
66
#include <arm_neon.h>
77

88
uint8x8_t test_shift_vshr(uint8x8_t a) {

‎clang/test/CodeGen/aarch64-neon-sm4-sm3.c

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Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
42
// RUN: -target-feature +sm4 -S -emit-llvm -o - %s \
53
// RUN: | FileCheck %s
64

75
// RUN: not %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
86
// RUN: -S -emit-llvm -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
97

8+
// REQUIRES: aarch64-registered-target || arm-registered-target
9+
1010
#include <arm_neon.h>
1111

1212
void test_vsm3partw1(uint32x4_t a, uint32x4_t b, uint32x4_t c) {

‎clang/test/CodeGen/aarch64-neon-tbl.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,7 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
53

6-
// Test new aarch64 intrinsics and types
4+
// REQUIRES: aarch64-registered-target || arm-registered-target
75

86
#include <arm_neon.h>
97

‎clang/test/CodeGen/aarch64-neon-vcadd.c

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Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
42
// RUN: -target-feature +v8.3a -target-feature +fullfp16 -S -emit-llvm -o - %s \
53
// RUN: | FileCheck %s
64

5+
// REQUIRES: aarch64-registered-target || arm-registered-target
6+
77
#include <arm_neon.h>
88

99
void foo16x4_rot90(float16x4_t a, float16x4_t b)

‎clang/test/CodeGen/aarch64-neon-vcmla.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,10 @@
1-
// REQUIRES: aarch64-registered-target
21
// RUN: %clang_cc1 -triple arm64-apple-ios -target-feature +neon \
32
// RUN: -target-feature +v8.3a \
43
// RUN: -target-feature +fullfp16 \
54
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -O1 | FileCheck %s
5+
6+
// REQUIRES: aarch64-registered-target
7+
68
#include <arm_neon.h>
79

810
// CHECK-LABEL: @test_vcmla_f16(

‎clang/test/CodeGen/aarch64-neon-vcombine.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,6 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
42

5-
// Test new aarch64 intrinsics and types
3+
// REQUIRES: aarch64-registered-target || arm-registered-target
64

75
#include <arm_neon.h>
86

‎clang/test/CodeGen/aarch64-neon-vget-hilo.c

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,8 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s \
53
// RUN: | opt -S -mem2reg | FileCheck %s
6-
// Test new aarch64 intrinsics and types
4+
5+
// REQUIRES: aarch64-registered-target || arm-registered-target
76

87
#include <arm_neon.h>
98

‎clang/test/CodeGen/aarch64-neon-vget.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-apple-darwin -target-feature +neon \
42
// RUN: -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s \
53
// RUN: | opt -S -mem2reg | FileCheck %s
64

5+
// REQUIRES: aarch64-registered-target || arm-registered-target
6+
77
#include <arm_neon.h>
88

99
// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_u8(<8 x i8> %a) #0 {

‎clang/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg -dce \
53
// RUN: | FileCheck %s
64

5+
// REQUIRES: aarch64-registered-target || arm-registered-target
6+
77
#include <arm_neon.h>
88

99
// Check float conversion is accepted for int argument

‎clang/test/CodeGen/aarch64-neon-vuqadd-float-conversion-warning.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -S -disable-O0-optnone -emit-llvm -o - %s 2>&1 | FileCheck %s
53

4+
// REQUIRES: aarch64-registered-target || arm-registered-target
5+
66
#include <arm_neon.h>
77

88
// Check float conversion is not accepted for unsigned int argument

‎clang/test/CodeGen/aarch64-poly-add.c

Lines changed: 2 additions & 1 deletion
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@@ -1,9 +1,10 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2-
// REQUIRES: aarch64-registered-target
32
// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
43
// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg \
54
// RUN: | FileCheck %s
65

6+
// REQUIRES: aarch64-registered-target
7+
78
#include <arm_neon.h>
89

910
// CHECK-LABEL: @test_vadd_p8(

‎clang/test/CodeGen/aarch64-poly128.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
1-
// REQUIRES: aarch64-registered-target
21
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
32
// RUN: -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - %s | opt -S -mem2reg \
43
// RUN: | FileCheck %s
54

5+
// REQUIRES: aarch64-registered-target
6+
67
// Test new aarch64 intrinsics with poly128
78
// FIXME: Currently, poly128_t equals to uint128, which will be spilt into
89
// two 64-bit GPR(eg X0, X1). Now moving data from X0, X1 to FPR128 will

‎clang/test/CodeGen/aarch64-poly64.c

Lines changed: 1 addition & 3 deletions
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@@ -1,10 +1,8 @@
1-
// REQUIRES: aarch64-registered-target || arm-registered-target
2-
31
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
42
// RUN: -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg \
53
// RUN: | FileCheck %s
64

7-
// Test new aarch64 intrinsics with poly64
5+
// REQUIRES: aarch64-registered-target || arm-registered-target
86

97
#include <arm_neon.h>
108

‎clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -mvscale-min=4 -mvscale-max=4 | FileCheck %s -D#VBITS=512 --check-prefixes=CHECK,CHECK512
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -mvscale-min=8 -mvscale-max=8 | FileCheck %s -D#VBITS=1024 --check-prefixes=CHECK,CHECK1024
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -mvscale-min=16 -mvscale-max=16 | FileCheck %s -D#VBITS=2048 --check-prefixes=CHECK,CHECK2048
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// REQUIRES: aarch64-registered-target
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// Examples taken from section "3.7.3.3 Behavior specific to SVE

‎clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp

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// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -mvscale-min=4 -mvscale-max=4 | FileCheck %s -D#VBITS=512 --check-prefixes=CHECK,CHECKWIDE
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// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -mvscale-min=8 -mvscale-max=8 | FileCheck %s -D#VBITS=1024 --check-prefixes=CHECK,CHECKWIDE
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// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -mvscale-min=16 -mvscale-max=16 | FileCheck %s -D#VBITS=2048 --check-prefixes=CHECK,CHECKWIDE
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// REQUIRES: aarch64-registered-target
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// Examples taken from section "3.7.3.3 Behavior specific to SVE

‎clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c

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// REQUIRES: aarch64-registered-target || arm-registered-target
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
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// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
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// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
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// REQUIRES: aarch64-registered-target || arm-registered-target
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#include <arm_sve.h>
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#ifdef SVE_OVERLOADED_FORMS

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