[test] Replace aarch64-arm-none-eabi with aarch64

Similar to 02e9441, but for llvm/test and one
lld/test/ELF test.

Author: MaskRay

lld/test/ELF/eh-frame-cfi-b-key.s

@@ -1,5 +1,5 @@
 // REQUIRES: aarch64
-// RUN: llvm-mc -filetype=obj -triple aarch64-arm-none-eabi %s -o %t.o
+// RUN: llvm-mc -filetype=obj -triple aarch64 %s -o %t.o
 // RUN: ld.lld %t.o -o %t --icf=all --eh-frame-hdr
 
 .globl _start

llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir

@@ -4,7 +4,7 @@
 # PR36345
 --- |
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-  target triple = "aarch64-arm-none-eabi"
+  target triple = "aarch64"
 
   ; Function Attrs: noinline nounwind optnone
   define void @fp16_to_gpr([2 x half], [2 x half]* %addr) {

llvm/test/CodeGen/AArch64/a55-fuse-address.mir

@@ -2,7 +2,7 @@
 # RUN: llc -o - %s -mtriple=aarch64 -run-pass=machine-scheduler -verify-machineinstrs | FileCheck %s
 --- |
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-  target triple = "aarch64-arm-none-eabi"
+  target triple = "aarch64"
 
   @a = dso_local global i32 2, align 4
   @b = dso_local global i32 4, align 4

llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll

@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple aarch64-arm-none-eabi  -mattr=+bf16 %s -o - | FileCheck %s
+; RUN: llc -mtriple aarch64  -mattr=+bf16 %s -o - | FileCheck %s
 
 define <2 x float> @test_vbfdot_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) {
 ; CHECK-LABEL: test_vbfdot_f32:

llvm/test/CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll

@@ -1,4 +1,4 @@
-; RUN: llc -mtriple aarch64-arm-none-eabi -asm-verbose=1 -mattr=+bf16 %s -o - | FileCheck %s
+; RUN: llc -mtriple aarch64 -asm-verbose=1 -mattr=+bf16 %s -o - | FileCheck %s
 
 %struct.bfloat16x4x2_t = type { [2 x <4 x bfloat>] }
 %struct.bfloat16x8x2_t = type { [2 x <8 x bfloat>] }

llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir

@@ -3,7 +3,7 @@
 # CHECK:     add     sp, sp, #16
 --- |
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-  target triple = "aarch64-arm-none-eabi"
+  target triple = "aarch64"
 
   define hidden i32 @foo(i32 %0) {
     %2 = alloca [4 x i32], align 4

llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll

@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O2 -mattr=+mops       | FileCheck %s --check-prefix=CHECK-MOPS
+; RUN: llc %s -o - -mtriple=aarch64 -O2 -mattr=+mops       | FileCheck %s --check-prefix=CHECK-MOPS
 
 declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)
 

llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll

@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O0 -global-isel=1 -global-isel-abort=1 -mattr=+mops,+mte  | FileCheck %s --check-prefix=GISel-O0
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi     -global-isel=1 -global-isel-abort=1 -mattr=+mops,+mte  | FileCheck %s --check-prefix=GISel
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O2 -mattr=+mops,+mte  | FileCheck %s --check-prefix=SDAG
+; RUN: llc %s -o - -mtriple=aarch64 -O0 -global-isel=1 -global-isel-abort=1 -mattr=+mops,+mte  | FileCheck %s --check-prefix=GISel-O0
+; RUN: llc %s -o - -mtriple=aarch64     -global-isel=1 -global-isel-abort=1 -mattr=+mops,+mte  | FileCheck %s --check-prefix=GISel
+; RUN: llc %s -o - -mtriple=aarch64 -O2 -mattr=+mops,+mte  | FileCheck %s --check-prefix=SDAG
 
 declare ptr @llvm.aarch64.mops.memset.tag(ptr, i8, i64)
 

llvm/test/CodeGen/AArch64/aarch64-mops.ll

@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O0 -global-isel=1 -global-isel-abort=1                    | FileCheck %s --check-prefixes=GISel-WITHOUT-MOPS,GISel-WITHOUT-MOPS-O0
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi     -global-isel=1 -global-isel-abort=1                    | FileCheck %s --check-prefixes=GISel-WITHOUT-MOPS,GISel-WITHOUT-MOPS-O3
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O0 -global-isel=1 -global-isel-abort=1 -mattr=+mops       | FileCheck %s --check-prefixes=GISel-MOPS,GISel-MOPS-O0
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi     -global-isel=1 -global-isel-abort=1 -mattr=+mops       | FileCheck %s --check-prefixes=GISel-MOPS,GISel-MOPS-O3
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O2                    | FileCheck %s --check-prefix=SDAG-WITHOUT-MOPS-O2
-; RUN: llc %s -o - -mtriple=aarch64-arm-none-eabi -O2 -mattr=+mops       | FileCheck %s --check-prefix=SDAG-MOPS-O2
+; RUN: llc %s -o - -mtriple=aarch64 -O0 -global-isel=1 -global-isel-abort=1                    | FileCheck %s --check-prefixes=GISel-WITHOUT-MOPS,GISel-WITHOUT-MOPS-O0
+; RUN: llc %s -o - -mtriple=aarch64     -global-isel=1 -global-isel-abort=1                    | FileCheck %s --check-prefixes=GISel-WITHOUT-MOPS,GISel-WITHOUT-MOPS-O3
+; RUN: llc %s -o - -mtriple=aarch64 -O0 -global-isel=1 -global-isel-abort=1 -mattr=+mops       | FileCheck %s --check-prefixes=GISel-MOPS,GISel-MOPS-O0
+; RUN: llc %s -o - -mtriple=aarch64     -global-isel=1 -global-isel-abort=1 -mattr=+mops       | FileCheck %s --check-prefixes=GISel-MOPS,GISel-MOPS-O3
+; RUN: llc %s -o - -mtriple=aarch64 -O2                    | FileCheck %s --check-prefix=SDAG-WITHOUT-MOPS-O2
+; RUN: llc %s -o - -mtriple=aarch64 -O2 -mattr=+mops       | FileCheck %s --check-prefix=SDAG-MOPS-O2
 
 declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)
 

llvm/test/CodeGen/AArch64/bf16-convert-intrinsics.ll

@@ -1,4 +1,4 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-arm-none-eabi -mattr=+neon -mattr=+bf16 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64 -mattr=+neon -mattr=+bf16 | FileCheck %s
 
 declare bfloat @llvm.aarch64.neon.bfcvt(float)
 declare <8 x bfloat> @llvm.aarch64.neon.bfcvtn(<4 x float>)

llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll

@@ -4,7 +4,7 @@
 ; FALLBACK: remark: <unknown>:0:0: unable to translate instruction: call: '  tail call void %p()' (in function: bti_enabled)
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; When BTI is enabled, all indirect tail-calls must use x16 or x17 (the intra
 ; procedure call scratch registers) to hold the address, as these instructions

llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-contract.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+complxnum,+neon -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; a * b + c
 define <4 x double> @mull_add(<4 x double> %a, <4 x double> %b, <4 x double> %c) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-fixed-fast.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+complxnum,+neon -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; a * b + c
 define <4 x double> @mull_add(<4 x double> %a, <4 x double> %b, <4 x double> %c) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; a * b + c
 define <vscale x 4 x double> @mull_add(<vscale x 4 x double> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; Expected to not transform
 define <vscale x 4 x half> @complex_add_v4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll

@@ -2,7 +2,7 @@
 ; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
 ; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16,+sve -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; Expected to not transform
 define <2 x half> @complex_add_v2f16(<2 x half> %a, <2 x half> %b) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; Expected to transform
 define <vscale x 4 x half> @complex_mul_v4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; Expected to not transform
 define <2 x half> @complex_mul_v2f16(<2 x half> %a, <2 x half> %b) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; Expected to transform
 define <vscale x 4 x float> @complex_add_v4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 
 ; Expected to transform

llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; Expected to transform
 define <vscale x 4 x float> @complex_mul_v4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; Expected to transform
 define <2 x float> @complex_mul_v2f32(<2 x float> %a, <2 x float> %b) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; Expected to transform
 define <vscale x 2 x double> @complex_add_v2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 
 ; Expected to transform

llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; Expected to transform
 define <vscale x 2 x double> @complex_mul_v2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; Expected to transform
 define <2 x double> @complex_mul_v2f64(<2 x double> %a, <2 x double> %b) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-mixed-cases.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; Expected to transform
 define <4 x float> @mul_mul(<4 x float> %a, <4 x float> %b, <4 x float> %c) {

llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+complxnum,+neon -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 ; Expected to transform
 ;   *p = (a * b);
 ;   return (a * b) * a;

llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 %"class.std::complex" = type { { double, double } }
 

llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+sve -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 %"class.std::complex" = type { { double, double } }
 

llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+complxnum,+neon -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 %"struct.std::complex" = type { { double, double } }
 

llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll

@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s --mattr=+complxnum,+neon,+fullfp16 -o - | FileCheck %s
 
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 ; Expected to transform
 define <4 x float> @simple_mul(<4 x float> %a, <4 x float> %b) {

llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir

@@ -19,7 +19,7 @@
  ; CHECK-NEXT: stack:
 
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-  target triple = "aarch64-arm-none-eabi"
+  target triple = "aarch64"
 
   %struct.S = type { i32, i32 }
 

llvm/test/CodeGen/AArch64/elim-dead-mi.mir

@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-arm-none-eabi -o - %s \
+# RUN: llc -mtriple=aarch64 -o - %s \
 # RUN: -run-pass dead-mi-elimination | FileCheck %s
 --- |
   @c = internal unnamed_addr global [3 x i8] zeroinitializer, align 4

llvm/test/CodeGen/AArch64/fast-isel-branch-uncond-debug.ll

@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-arm-none-eabi -O1 -opt-bisect-limit=2 -o - %s  2> /dev/null | FileCheck %s
+; RUN: llc -mtriple=aarch64 -O1 -opt-bisect-limit=2 -o - %s  2> /dev/null | FileCheck %s
 
 define dso_local i32 @a() #0 !dbg !7 {
 entry:

llvm/test/CodeGen/AArch64/fptosi-strictfp.ll

@@ -1,6 +1,6 @@
 ; RUN: llc < %s | FileCheck %s
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 define i128 @test_fixtfti(fp128 %ld) #0 {
 ; CHECK-LABEL: test_fixtfti:

llvm/test/CodeGen/AArch64/global-merge-minsize.ll

@@ -1,7 +1,7 @@
 ; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-arm-none-eabi"
+target triple = "aarch64"
 
 @global0 = dso_local local_unnamed_addr global i32 0, align 4
 @global1 = dso_local local_unnamed_addr global i32 0, align 4

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll

@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
+; RUN: aarch64 %s -o - | FileCheck %s --check-prefixes CHECK,V8A
 ; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
+; RUN-V83A: aarch64 -mattr=+v8.3a %s -o - > %t
 ; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
 
 ; Function a's outlining candidate contains a sp modifying add without a

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll

@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
+; RUN: aarch64 %s -o - | FileCheck %s --check-prefixes CHECK,V8A
 ; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
+; RUN-V83A: aarch64 -mattr=+v8.3a %s -o - > %t
 ; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
 
 define void @a() "sign-return-address"="all" {

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll

@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
+; RUN: aarch64 %s -o - | FileCheck %s --check-prefixes CHECK,V8A
 ; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
+; RUN-V83A: aarch64 -mattr=+v8.3a %s -o - > %t
 ; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
 
 define i64 @a(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir

@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-arm-none-eabi -run-pass=prologepilog \
+# RUN: llc -mtriple=aarch64 -run-pass=prologepilog \
 # RUN: -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
 
 # Check that we save LR to a callee-saved register when possible.

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll

@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
+; RUN: aarch64 %s -o - | FileCheck %s --check-prefixes CHECK,V8A
 ; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
+; RUN-V83A: aarch64 -mattr=+v8.3a %s -o - > %t
 ; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
 
 define void @a() "sign-return-address"="all" {

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-a.ll

@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
+; RUN: aarch64 %s -o - | FileCheck %s --check-prefixes CHECK,V8A
 ; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
+; RUN-V83A: aarch64 -mattr=+v8.3a %s -o - > %t
 ; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
 
 define void @a() "sign-return-address"="all" "sign-return-address-key"="a_key" nounwind {

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-same-key-b.ll

@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN: aarch64-arm-none-eabi %s -o - | FileCheck %s --check-prefixes CHECK,V8A
+; RUN: aarch64 %s -o - | FileCheck %s --check-prefixes CHECK,V8A
 ; RUN-V83A: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
-; RUN-V83A: aarch64-arm-none-eabi -mattr=+v8.3a %s -o - > %t
+; RUN-V83A: aarch64 -mattr=+v8.3a %s -o - > %t
 ; RUN-V83A: FileCheck --check-prefixes CHECK,V83A < %t %s
 
 define void @a() "sign-return-address"="all" "sign-return-address-key"="b_key" nounwind {

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.ll

@@ -1,4 +1,4 @@
-; RUN: llc -mtriple aarch64-arm-none-eabi -enable-machine-outliner \
+; RUN: llc -mtriple aarch64 -enable-machine-outliner \
 ; RUN:  -verify-machineinstrs %s -o - | FileCheck %s
 
 @v = common dso_local global ptr null, align 8