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[DAGComb] Do not turn insert_elt into shuffle for single elt vectors. #1287

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Merged
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Jun 2, 2020
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[DAGComb] Do not turn insert_elt into shuffle for single elt vectors. #1287

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4 changes: 4 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16826,6 +16826,10 @@ SDValue DAGCombiner::combineInsertEltToShuffle(SDNode *N, unsigned InsIndex) {
EVT SubVecVT = SubVec.getValueType();
EVT VT = DestVec.getValueType();
unsigned NumSrcElts = SubVecVT.getVectorNumElements();
// If the source only has a single vector element, the cost of creating adding
// it to a vector is likely to exceed the cost of a insert_vector_elt.
if (NumSrcElts == 1)
return SDValue();
unsigned ExtendRatio = VT.getSizeInBits() / SubVecVT.getSizeInBits();
unsigned NumMaskVals = ExtendRatio * NumSrcElts;

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14 changes: 13 additions & 1 deletion llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
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Expand Up @@ -200,7 +200,19 @@ define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {
; CHECK-LABEL: ins1f2:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: zip1 v0.2d, v1.2d, v0.2d
; CHECK-NEXT: mov v1.d[1], v0.d[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
%tmp3 = extractelement <1 x double> %tmp1, i32 0
%tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
ret <2 x double> %tmp4
}

define <2 x double> @ins1f2_args_flipped(<2 x double> %tmp2, <1 x double> %tmp1) {
; CHECK-LABEL: ins1f2_args_flipped:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: mov v0.d[1], v1.d[0]
; CHECK-NEXT: ret
%tmp3 = extractelement <1 x double> %tmp1, i32 0
%tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
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35 changes: 35 additions & 0 deletions llvm/test/CodeGen/AArch64/vector-insert-shuffle-cycle.ll
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@@ -0,0 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc %s -o - | FileCheck %s

target triple = "arm64-apple-ios13.4.0"

; Make we do not get stuck in a cycle in DAGCombiner.

define void @test(i1 %c, <1 x double>* %ptr) {
; CHECK-LABEL: test:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi d0, #0000000000000000
; CHECK-NEXT: tbz w0, #0, LBB0_2
; CHECK-NEXT: ; %bb.1: ; %bb1
; CHECK-NEXT: ldr d0, [x1]
; CHECK-NEXT: LBB0_2: ; %bb2
; CHECK-NEXT: ldr q1, [x8]
; CHECK-NEXT: mov.d v1[0], v0[0]
; CHECK-NEXT: str q1, [x8]
; CHECK-NEXT: ret
entry:
br i1 %c, label %bb1, label %bb2

bb1:
%lv1 = load <1 x double>, <1 x double>* %ptr, align 16
br label %bb2

bb2:
%p = phi <1 x double> [ %lv1, %bb1 ], [ zeroinitializer, %entry ]
%vecext19 = extractelement <1 x double> %p, i32 0
%arrayidx21 = getelementptr inbounds [4 x <4 x double>], [4 x <4 x double>]* undef, i64 0, i64 3
%lv2 = load <4 x double>, <4 x double>* %arrayidx21, align 16
%vecins22 = insertelement <4 x double> %lv2, double %vecext19, i32 2
store <4 x double> %vecins22, <4 x double>* %arrayidx21, align 16
ret void
}