Pick [AArch64] Add custom lowering for load <3 x i8>. #8078
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Add custom combine to lower load <3 x i8> as the more efficient sequence below: ldrb wX, [x0, swiftlang#2] ldrh wY, [x0] orr wX, wY, wX, lsl swiftlang#16 fmov s0, wX At the moment, there are almost no cases in which such vector operations will be generated automatically. The motivating case is non-power-of-2 SLP vectorization: llvm#77790 (cherry-picked from d1e162e)
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@swift-ci please test |
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@swift-ci please test llvm |
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