[IRGenSIL] When emitting a shadow copy, honour the layout.

[dcci]

This code was ad-hoc trying to reconstruct the layout. Ask TypeInfo
instead, as it knows what's the right thing to do.
This allows to print field of classes nested inside classes correctly
in lldb (SR-6791).

rdar://problem/36518505

[dcci]

Bonus, this makes the code easier to read/shorter.

[dcci]

@swift-ci test and merge

[vedantk]

Shouldn't we still store a shadow value for the phi somewhere? Can we keep checking for that?

[dcci]

I'm not sure we should emit a shadow value for the PHI.
If anything, we should emit a shadow value for the args of the PHI node, and I think in this particular case it's not really required?

[dcci]

For reference, this is the generated IR:

define swiftcc void @"$S4main1fyySiSgF"(i64, i8) #2 !dbg !48 {
entry:
  %debug.copy = alloca %TSiSg, align 8
  call void @llvm.dbg.declare(metadata %TSiSg* %debug.copy, metadata !52, metadata !DIExpression()),
!dbg !53
  %val.addr = alloca i64, align 8
  call void @llvm.dbg.declare(metadata i64* %val.addr, metadata !54, metadata !DIExpression()), !dbg
!57
  %2 = alloca %TSi, align 8
  %3 = trunc i8 %1 to i1
  %4 = bitcast %TSiSg* %debug.copy to i8*, !dbg !58
  call void @llvm.lifetime.start.p0i8(i64 9, i8* %4), !dbg !58
  %5 = bitcast %TSiSg* %debug.copy to i64*, !dbg !58
  store i64 %0, i64* %5, align 8, !dbg !58
  %6 = getelementptr inbounds %TSiSg, %TSiSg* %debug.copy, i32 0, i32 1, !dbg !58
  %7 = bitcast [1 x i8]* %6 to i1*, !dbg !58
  store i1 %3, i1* %7, align 8, !dbg !58
  br i1 %3, label %9, label %8, !dbg !59

; <label>:8:                                      ; preds = %entry
  br label %10, !dbg !59

; <label>:9:                                      ; preds = %entry
  br label %16, !dbg !59

; <label>:10:                                     ; preds = %8
  %11 = phi i64 [ %0, %8 ], !dbg !60
  store i64 %11, i64* %val.addr, align 8, !dbg !60
  br label %12, !dbg !59

[dcci]

I and Vedant discussed this offline.
We agreed that this code used to check that we store a value to the alloca we create, and now the test doesn't anymore. I'll add the correct check lines, i.e.

 // CHECK: %5 = bitcast %TSiSg* %debug.copy to i64*, !dbg !58
 // CHECK: store i64 %0, i64* %5, align 8, !dbg !58