[Frontend] Add -emit-irgen option to driver and frontend.

include/swift/AST/IRGenOptions.h

@@ -40,7 +40,10 @@ enum class IRGenOutputKind : unsigned {
   Module,
 
   /// Generate an LLVM module and write it out as LLVM assembly.
-  LLVMAssembly,
+  LLVMAssemblyBeforeOptimization,
+
+  /// Generate an LLVM module and write it out as LLVM assembly.
+  LLVMAssemblyAfterOptimization,
 
   /// Generate an LLVM module and write it out as LLVM bitcode.
   LLVMBitcode,
@@ -354,7 +357,8 @@ class IRGenOptions {
   JITDebugArtifact DumpJIT = JITDebugArtifact::None;
 
   IRGenOptions()
-      : DWARFVersion(2), OutputKind(IRGenOutputKind::LLVMAssembly),
+      : DWARFVersion(2),
+        OutputKind(IRGenOutputKind::LLVMAssemblyAfterOptimization),
         Verify(true), OptMode(OptimizationMode::NotSet),
         Sanitizers(OptionSet<SanitizerKind>()),
         SanitizersWithRecoveryInstrumentation(OptionSet<SanitizerKind>()),
@@ -401,7 +405,8 @@ class IRGenOptions {
     if (HasValueNamesSetting) {
       return ValueNames;
     } else {
-      return OutputKind == IRGenOutputKind::LLVMAssembly;
+      return OutputKind == IRGenOutputKind::LLVMAssemblyBeforeOptimization ||
+             OutputKind == IRGenOutputKind::LLVMAssemblyAfterOptimization;
     }
   }
 

include/swift/Frontend/FrontendOptions.h

@@ -134,7 +134,8 @@ class FrontendOptions {
     REPL,      ///< REPL mode
 
     EmitAssembly, ///< Emit assembly
-    EmitIR,       ///< Emit LLVM IR
+    EmitIRGen,    ///< Emit LLVM IR before LLVM optimizations
+    EmitIR,       ///< Emit LLVM IR after LLVM optimizations
     EmitBC,       ///< Emit LLVM BC
     EmitObject,   ///< Emit object file
 

include/swift/Option/Options.td

@@ -907,8 +907,11 @@ def emit_assembly : Flag<["-"], "emit-assembly">,
 def emit_bc : Flag<["-"], "emit-bc">,
   HelpText<"Emit LLVM BC file(s)">, ModeOpt,
   Flags<[FrontendOption, NoInteractiveOption, DoesNotAffectIncrementalBuild]>;
+def emit_irgen : Flag<["-"], "emit-irgen">,
+  HelpText<"Emit LLVM IR file(s) before LLVM optimizations">, ModeOpt,
+  Flags<[FrontendOption, NoInteractiveOption, DoesNotAffectIncrementalBuild]>;
 def emit_ir : Flag<["-"], "emit-ir">,
-  HelpText<"Emit LLVM IR file(s)">, ModeOpt,
+  HelpText<"Emit LLVM IR file(s) after LLVM optimizations">, ModeOpt,
   Flags<[FrontendOption, NoInteractiveOption, DoesNotAffectIncrementalBuild]>;
 def emit_sil : Flag<["-"], "emit-sil">,
   HelpText<"Emit canonical SIL file(s)">, ModeOpt,

lib/Driver/Driver.cpp

@@ -1504,6 +1504,7 @@ void Driver::buildOutputInfo(const ToolChain &TC, const DerivedArgList &Args,
       OI.CompilerOutputType = file_types::TY_RawSIB;
       break;
 
+    case options::OPT_emit_irgen:
     case options::OPT_emit_ir:
       OI.CompilerOutputType = file_types::TY_LLVM_IR;
       break;

lib/Frontend/ArgsToFrontendOptionsConverter.cpp

@@ -386,6 +386,8 @@ ArgsToFrontendOptionsConverter::determineRequestedAction(const ArgList &args) {
     return FrontendOptions::ActionType::EmitObject;
   if (Opt.matches(OPT_emit_assembly))
     return FrontendOptions::ActionType::EmitAssembly;
+  if (Opt.matches(OPT_emit_irgen))
+    return FrontendOptions::ActionType::EmitIRGen;
   if (Opt.matches(OPT_emit_ir))
     return FrontendOptions::ActionType::EmitIR;
   if (Opt.matches(OPT_emit_bc))

lib/Frontend/CompilerInvocation.cpp

@@ -179,8 +179,10 @@ setIRGenOutputOptsFromFrontendOptions(IRGenOptions &IRGenOpts,
   // Set the OutputKind for the given Action.
   IRGenOpts.OutputKind = [](FrontendOptions::ActionType Action) {
     switch (Action) {
+    case FrontendOptions::ActionType::EmitIRGen:
+      return IRGenOutputKind::LLVMAssemblyBeforeOptimization;
     case FrontendOptions::ActionType::EmitIR:
-      return IRGenOutputKind::LLVMAssembly;
+      return IRGenOutputKind::LLVMAssemblyAfterOptimization;
     case FrontendOptions::ActionType::EmitBC:
       return IRGenOutputKind::LLVMBitcode;
     case FrontendOptions::ActionType::EmitAssembly:

lib/Frontend/FrontendOptions.cpp

@@ -59,6 +59,7 @@ bool FrontendOptions::needsProperModuleName(ActionType action) {
   case ActionType::PrintFeature:
     return false;
   case ActionType::EmitAssembly:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitObject:
@@ -119,6 +120,7 @@ bool FrontendOptions::doesActionRequireSwiftStandardLibrary(ActionType action) {
   case ActionType::Immediate:
   case ActionType::REPL:
   case ActionType::EmitAssembly:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitObject:
@@ -162,6 +164,7 @@ bool FrontendOptions::doesActionRequireInputs(ActionType action) {
   case ActionType::EmitSIB:
   case ActionType::Immediate:
   case ActionType::EmitAssembly:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitObject:
@@ -203,6 +206,7 @@ bool FrontendOptions::doesActionPerformEndOfPipelineActions(ActionType action) {
   case ActionType::EmitSIB:
   case ActionType::Immediate:
   case ActionType::EmitAssembly:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitObject:
@@ -287,6 +291,7 @@ FrontendOptions::formatForPrincipalOutputFileForAction(ActionType action) {
   case ActionType::EmitAssembly:
     return TY_Assembly;
 
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
     return TY_LLVM_IR;
 
@@ -339,6 +344,7 @@ bool FrontendOptions::canActionEmitDependencies(ActionType action) {
   case ActionType::EmitSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitAssembly:
@@ -382,6 +388,7 @@ bool FrontendOptions::canActionEmitReferenceDependencies(ActionType action) {
   case ActionType::EmitSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitAssembly:
@@ -424,6 +431,7 @@ bool FrontendOptions::canActionEmitModuleSummary(ActionType action) {
     return false;
   case ActionType::EmitSIL:
   case ActionType::EmitSIB:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitAssembly:
@@ -464,6 +472,7 @@ bool FrontendOptions::canActionEmitObjCHeader(ActionType action) {
   case ActionType::EmitSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitAssembly:
@@ -505,6 +514,7 @@ bool FrontendOptions::canActionEmitLoadedModuleTrace(ActionType action) {
   case ActionType::EmitSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitAssembly:
@@ -546,6 +556,7 @@ bool FrontendOptions::canActionEmitModule(ActionType action) {
   case ActionType::EmitSIL:
   case ActionType::EmitSIBGen:
   case ActionType::EmitSIB:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitAssembly:
@@ -591,6 +602,7 @@ bool FrontendOptions::canActionEmitInterface(ActionType action) {
   case ActionType::EmitModuleOnly:
   case ActionType::EmitSIL:
   case ActionType::EmitSIB:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitAssembly:
@@ -620,6 +632,7 @@ bool FrontendOptions::doesActionProduceOutput(ActionType action) {
   case ActionType::EmitSIB:
   case ActionType::EmitModuleOnly:
   case ActionType::EmitAssembly:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitObject:
@@ -674,6 +687,7 @@ bool FrontendOptions::doesActionProduceTextualOutput(ActionType action) {
   case ActionType::EmitSILGen:
   case ActionType::EmitSIL:
   case ActionType::EmitAssembly:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::DumpTypeInfo:
   case ActionType::DumpPCM:
@@ -717,6 +731,7 @@ bool FrontendOptions::doesActionGenerateSIL(ActionType action) {
   case ActionType::Immediate:
   case ActionType::REPL:
   case ActionType::EmitAssembly:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitObject:
@@ -758,6 +773,7 @@ bool FrontendOptions::doesActionGenerateIR(ActionType action) {
     return false;
   case ActionType::Immediate:
   case ActionType::REPL:
+  case ActionType::EmitIRGen:
   case ActionType::EmitIR:
   case ActionType::EmitBC:
   case ActionType::EmitAssembly:

lib/FrontendTool/FrontendTool.cpp

@@ -1232,6 +1232,7 @@ static bool performAction(CompilerInstance &Instance,
   case FrontendOptions::ActionType::MergeModules:
   case FrontendOptions::ActionType::Immediate:
   case FrontendOptions::ActionType::EmitAssembly:
+  case FrontendOptions::ActionType::EmitIRGen:
   case FrontendOptions::ActionType::EmitIR:
   case FrontendOptions::ActionType::EmitBC:
   case FrontendOptions::ActionType::EmitObject:

lib/IRGen/IRGen.cpp

@@ -537,6 +537,10 @@ bool swift::performLLVM(const IRGenOptions &Opts,
       RawOS->clear_error();
       return true;
     }
+    if (Opts.OutputKind == IRGenOutputKind::LLVMAssemblyBeforeOptimization) {
+      Module->print(RawOS.getValue(), nullptr);
+      return false;
+    }
   } else {
     assert(Opts.OutputKind == IRGenOutputKind::Module && "no output specified");
   }
@@ -569,9 +573,11 @@ bool swift::compileAndWriteLLVM(llvm::Module *module,
 
   // Set up the final emission passes.
   switch (opts.OutputKind) {
+  case IRGenOutputKind::LLVMAssemblyBeforeOptimization:
+    llvm_unreachable("Should be handled earlier.");
   case IRGenOutputKind::Module:
     break;
-  case IRGenOutputKind::LLVMAssembly:
+  case IRGenOutputKind::LLVMAssemblyAfterOptimization:
     EmitPasses.add(createPrintModulePass(out));
     break;
   case IRGenOutputKind::LLVMBitcode: {

test/Frontend/emit-irgen.swift

@@ -0,0 +1,4 @@
+// RUN: %target-swift-frontend -emit-irgen %s | %FileCheck %s
+
+// CHECK: define{{.*}} swiftcc void @"$s4main5helloyyF"
+public func hello() { }

tools/sil-llvm-gen/SILLLVMGen.cpp

@@ -88,17 +88,17 @@ static llvm::cl::opt<std::string>
 static llvm::cl::opt<bool>
     PerformWMO("wmo", llvm::cl::desc("Enable whole-module optimizations"));
 
-static llvm::cl::opt<IRGenOutputKind>
-    OutputKind("output-kind", llvm::cl::desc("Type of output to produce"),
-               llvm::cl::values(clEnumValN(IRGenOutputKind::LLVMAssembly,
-                                           "llvm-as", "Emit llvm assembly"),
-                                clEnumValN(IRGenOutputKind::LLVMBitcode,
-                                           "llvm-bc", "Emit llvm bitcode"),
-                                clEnumValN(IRGenOutputKind::NativeAssembly,
-                                           "as", "Emit native assembly"),
-                                clEnumValN(IRGenOutputKind::ObjectFile,
-                                           "object", "Emit an object file")),
-               llvm::cl::init(IRGenOutputKind::ObjectFile));
+static llvm::cl::opt<IRGenOutputKind> OutputKind(
+    "output-kind", llvm::cl::desc("Type of output to produce"),
+    llvm::cl::values(clEnumValN(IRGenOutputKind::LLVMAssemblyAfterOptimization,
+                                "llvm-as", "Emit llvm assembly"),
+                     clEnumValN(IRGenOutputKind::LLVMBitcode, "llvm-bc",
+                                "Emit llvm bitcode"),
+                     clEnumValN(IRGenOutputKind::NativeAssembly, "as",
+                                "Emit native assembly"),
+                     clEnumValN(IRGenOutputKind::ObjectFile, "object",
+                                "Emit an object file")),
+    llvm::cl::init(IRGenOutputKind::ObjectFile));
 
 static llvm::cl::opt<bool>
     DisableLegacyTypeInfo("disable-legacy-type-info",