IRGen: Avoid generating LLVM switches when brs will do. #5092
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FastISel doesn't like switch, and it's generally more compact code gen to build conditionals for two-target branches instead of switching all the time. There are many popular two-tag enums (Optional, someday Bool, Either) and this should greatly improve the potential for FastISel to kick in at -Onone.
rdar://problem/27476935