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[IRGen] Always load extra tag bits as full bytes in CVW to avoid elem… #74952

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Merged
merged 1 commit into from
Jul 3, 2024

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drexin
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@drexin drexin commented Jul 3, 2024

…ination of masking

rdar://129627898

LLVM expects integer types of fractional byte sizes to have been written as those types as well, so it expects all unused bytes to be 0. Since we are using the unused extra tag bits to store tags of outer enums, that assumption does not hold here. In regular witnesses, the outer enum would mask out those bytes before checking the tag of the inner enum. In CVW we can't do that, so we have to apply the mask ourselves. To guarantee the mask does not get optimized out, we have to use full bytes instead of fractionals.

…ination of masking

rdar://129627898

LLVM expects integer types of fractional byte sizes to have been written as those types as well, so it expects all unused bytes to be 0.
Since we are using the unused extra tag bits to store tags of outer enums, that assumption does not hold here. In regular witnesses,
the outer enum would mask out those bytes before checking the tag of the inner enum. In CVW we can't do that, so we have to apply the
mask ourselves. To guarantee the mask does not get optimized out, we have to use full bytes instead of fractionals.
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drexin commented Jul 3, 2024

@swift-ci smoke test

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lgtm. thanks

@drexin drexin merged commit 66a5329 into swiftlang:main Jul 3, 2024
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@drexin drexin deleted the wip-129627898 branch July 3, 2024 23:56
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2 participants