Fix IRGen/condfail.sil on s390x #8720
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Test change only, looks reasonable to me. @swift-ci Please test |
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Oops, I didn't realize this was for 3.1-branch... |
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On s390x, traps are supported as legal DAG opcodes and "j .+2" are generated for them.
https://reviews.llvm.org/D21155
Fix is the same as #8719 and this PR is for swift-3.1-branch.