@@ -36,13 +36,9 @@ define i32 @add_select_cmp_and2(i32 %in) {
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define i32 @add_select_cmp_and3 (i32 %in ) {
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; CHECK-LABEL: @add_select_cmp_and3(
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- ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
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- ; CHECK-NEXT: [[TEMP:%.*]] = mul nuw nsw i32 [[TMP1]], 72
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- ; CHECK-NEXT: [[BITOP2:%.*]] = and i32 [[IN]], 4
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- ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[BITOP2]], 0
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- ; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i32 0, i32 288
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- ; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[TEMP]], [[SEL2]]
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- ; CHECK-NEXT: ret i32 [[OUT]]
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+ ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 7
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+ ; CHECK-NEXT: [[TEMP1:%.*]] = mul nuw nsw i32 [[TMP1]], 72
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+ ; CHECK-NEXT: ret i32 [[TEMP1]]
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;
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%bitop0 = and i32 %in , 1
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%cmp0 = icmp eq i32 %bitop0 , 0
@@ -60,12 +56,9 @@ define i32 @add_select_cmp_and3(i32 %in) {
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define i32 @add_select_cmp_and4 (i32 %in ) {
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; CHECK-LABEL: @add_select_cmp_and4(
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- ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
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- ; CHECK-NEXT: [[OUT:%.*]] = mul nuw nsw i32 [[TMP1]], 72
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- ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[IN]], 12
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- ; CHECK-NEXT: [[TEMP3:%.*]] = mul nuw nsw i32 [[TMP2]], 72
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- ; CHECK-NEXT: [[OUT1:%.*]] = or disjoint i32 [[OUT]], [[TEMP3]]
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- ; CHECK-NEXT: ret i32 [[OUT1]]
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+ ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[IN:%.*]], 15
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+ ; CHECK-NEXT: [[TEMP2:%.*]] = mul nuw nsw i32 [[TMP2]], 72
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+ ; CHECK-NEXT: ret i32 [[TEMP2]]
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;
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%bitop0 = and i32 %in , 1
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%cmp0 = icmp eq i32 %bitop0 , 0
@@ -361,6 +354,103 @@ define i64 @mask_select_types_1(i64 %in) {
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ret i64 %out
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}
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+ define i32 @add_select_cmp_mixed1 (i32 %in ) {
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+ ; CHECK-LABEL: @add_select_cmp_mixed1(
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+ ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
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+ ; CHECK-NEXT: [[OUT:%.*]] = mul nuw nsw i32 [[TMP1]], 72
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+ ; CHECK-NEXT: ret i32 [[OUT]]
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+ ;
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+ %mask = and i32 %in , 1
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+ %sel0 = mul i32 %mask , 72
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+ %bitop1 = and i32 %in , 2
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+ %cmp1 = icmp eq i32 %bitop1 , 0
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+ %sel1 = select i1 %cmp1 , i32 0 , i32 144
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+ %out = or disjoint i32 %sel0 , %sel1
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+ ret i32 %out
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+ }
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+
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+ define i32 @add_select_cmp_mixed2 (i32 %in ) {
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+ ; CHECK-LABEL: @add_select_cmp_mixed2(
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+ ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
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+ ; CHECK-NEXT: [[OUT:%.*]] = mul nuw nsw i32 [[TMP1]], 72
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+ ; CHECK-NEXT: ret i32 [[OUT]]
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+ ;
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+ %bitop0 = and i32 %in , 1
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+ %cmp0 = icmp eq i32 %bitop0 , 0
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+ %mask = and i32 %in , 2
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+ %sel0 = select i1 %cmp0 , i32 0 , i32 72
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+ %sel1 = mul i32 %mask , 72
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+ %out = or disjoint i32 %sel0 , %sel1
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+ ret i32 %out
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+ }
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+
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+ define i32 @add_select_cmp_and_mul (i32 %in ) {
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+ ; CHECK-LABEL: @add_select_cmp_and_mul(
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+ ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
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+ ; CHECK-NEXT: [[OUT:%.*]] = mul nuw nsw i32 [[TMP1]], 72
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+ ; CHECK-NEXT: ret i32 [[OUT]]
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+ ;
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+ %mask0 = and i32 %in , 1
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+ %sel0 = mul i32 %mask0 , 72
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+ %mask1 = and i32 %in , 2
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+ %sel1 = mul i32 %mask1 , 72
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+ %out = or disjoint i32 %sel0 , %sel1
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+ ret i32 %out
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+ }
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+
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+ define i32 @add_select_cmp_mixed2_mismatch (i32 %in ) {
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+ ; CHECK-LABEL: @add_select_cmp_mixed2_mismatch(
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+ ; CHECK-NEXT: [[BITOP0:%.*]] = and i32 [[IN:%.*]], 1
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+ ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[BITOP0]], 0
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+ ; CHECK-NEXT: [[MASK:%.*]] = and i32 [[IN]], 2
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+ ; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 0, i32 73
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+ ; CHECK-NEXT: [[SEL1:%.*]] = mul nuw nsw i32 [[MASK]], 72
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+ ; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[SEL0]], [[SEL1]]
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+ ; CHECK-NEXT: ret i32 [[OUT]]
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+ ;
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+ %bitop0 = and i32 %in , 1
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+ %cmp0 = icmp eq i32 %bitop0 , 0
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+ %mask = and i32 %in , 2
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+ %sel0 = select i1 %cmp0 , i32 0 , i32 73
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+ %sel1 = mul i32 %mask , 72
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+ %out = or disjoint i32 %sel0 , %sel1
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+ ret i32 %out
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+ }
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+
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+ define i32 @add_select_cmp_and_mul_mismatch (i32 %in ) {
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+ ; CHECK-LABEL: @add_select_cmp_and_mul_mismatch(
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+ ; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[IN:%.*]] to i1
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+ ; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[TMP1]], i32 73, i32 0
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+ ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[IN]], 2
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+ ; CHECK-NEXT: [[SEL1:%.*]] = mul nuw nsw i32 [[MASK1]], 72
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+ ; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[SEL0]], [[SEL1]]
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+ ; CHECK-NEXT: ret i32 [[OUT]]
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+ ;
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+ %mask0 = and i32 %in , 1
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+ %sel0 = mul i32 %mask0 , 73
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+ %mask1 = and i32 %in , 2
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+ %sel1 = mul i32 %mask1 , 72
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+ %out = or disjoint i32 %sel0 , %sel1
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+ ret i32 %out
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+ }
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+
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+ define i32 @and_mul_non_disjoint (i32 %in ) {
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+ ; CHECK-LABEL: @and_mul_non_disjoint(
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+ ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 2
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+ ; CHECK-NEXT: [[OUT:%.*]] = mul nuw nsw i32 [[TMP1]], 72
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+ ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[IN]], 4
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+ ; CHECK-NEXT: [[SEL1:%.*]] = mul nuw nsw i32 [[MASK1]], 72
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+ ; CHECK-NEXT: [[OUT1:%.*]] = or i32 [[OUT]], [[SEL1]]
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+ ; CHECK-NEXT: ret i32 [[OUT1]]
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+ ;
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+ %mask0 = and i32 %in , 2
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+ %sel0 = mul i32 %mask0 , 72
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+ %mask1 = and i32 %in , 4
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+ %sel1 = mul i32 %mask1 , 72
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+ %out = or i32 %sel0 , %sel1
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+ ret i32 %out
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+ }
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+
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CONSTSPLAT: {{.*}}
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; CONSTVEC: {{.*}}
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