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RKSimonRKSimon
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[DAG] Add SelectionDAG::getShiftAmountConstant APInt variant (llvm#81484)
Asserts that the shift amount is in range and update ExpandShiftByConstant to use getShiftAmountConstant (and legal shift amount types).
1 parent d2ccf33 commit d30e941

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3 files changed

+40
-27
lines changed

3 files changed

+40
-27
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAG.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -668,6 +668,8 @@ class SelectionDAG {
668668
bool isTarget = false);
669669
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL,
670670
bool LegalTypes = true);
671+
SDValue getShiftAmountConstant(const APInt &Val, EVT VT, const SDLoc &DL,
672+
bool LegalTypes = true);
671673
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL,
672674
bool isTarget = false);
673675

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 32 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -2824,25 +2824,26 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
28242824
EVT NVT = InL.getValueType();
28252825
unsigned VTBits = N->getValueType(0).getSizeInBits();
28262826
unsigned NVTBits = NVT.getSizeInBits();
2827-
EVT ShTy = N->getOperand(1).getValueType();
28282827

28292828
if (N->getOpcode() == ISD::SHL) {
28302829
if (Amt.uge(VTBits)) {
28312830
Lo = Hi = DAG.getConstant(0, DL, NVT);
28322831
} else if (Amt.ugt(NVTBits)) {
28332832
Lo = DAG.getConstant(0, DL, NVT);
2834-
Hi = DAG.getNode(ISD::SHL, DL,
2835-
NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2833+
Hi = DAG.getNode(ISD::SHL, DL, NVT, InL,
2834+
DAG.getShiftAmountConstant(Amt - NVTBits, NVT, DL));
28362835
} else if (Amt == NVTBits) {
28372836
Lo = DAG.getConstant(0, DL, NVT);
28382837
Hi = InL;
28392838
} else {
2840-
Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
2841-
Hi = DAG.getNode(ISD::OR, DL, NVT,
2842-
DAG.getNode(ISD::SHL, DL, NVT, InH,
2843-
DAG.getConstant(Amt, DL, ShTy)),
2844-
DAG.getNode(ISD::SRL, DL, NVT, InL,
2845-
DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2839+
Lo = DAG.getNode(ISD::SHL, DL, NVT, InL,
2840+
DAG.getShiftAmountConstant(Amt, NVT, DL));
2841+
Hi = DAG.getNode(
2842+
ISD::OR, DL, NVT,
2843+
DAG.getNode(ISD::SHL, DL, NVT, InH,
2844+
DAG.getShiftAmountConstant(Amt, NVT, DL)),
2845+
DAG.getNode(ISD::SRL, DL, NVT, InL,
2846+
DAG.getShiftAmountConstant(-Amt + NVTBits, NVT, DL)));
28462847
}
28472848
return;
28482849
}
@@ -2851,43 +2852,47 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
28512852
if (Amt.uge(VTBits)) {
28522853
Lo = Hi = DAG.getConstant(0, DL, NVT);
28532854
} else if (Amt.ugt(NVTBits)) {
2854-
Lo = DAG.getNode(ISD::SRL, DL,
2855-
NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2855+
Lo = DAG.getNode(ISD::SRL, DL, NVT, InH,
2856+
DAG.getShiftAmountConstant(Amt - NVTBits, NVT, DL));
28562857
Hi = DAG.getConstant(0, DL, NVT);
28572858
} else if (Amt == NVTBits) {
28582859
Lo = InH;
28592860
Hi = DAG.getConstant(0, DL, NVT);
28602861
} else {
2861-
Lo = DAG.getNode(ISD::OR, DL, NVT,
2862-
DAG.getNode(ISD::SRL, DL, NVT, InL,
2863-
DAG.getConstant(Amt, DL, ShTy)),
2864-
DAG.getNode(ISD::SHL, DL, NVT, InH,
2865-
DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2866-
Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2862+
Lo = DAG.getNode(
2863+
ISD::OR, DL, NVT,
2864+
DAG.getNode(ISD::SRL, DL, NVT, InL,
2865+
DAG.getShiftAmountConstant(Amt, NVT, DL)),
2866+
DAG.getNode(ISD::SHL, DL, NVT, InH,
2867+
DAG.getShiftAmountConstant(-Amt + NVTBits, NVT, DL)));
2868+
Hi = DAG.getNode(ISD::SRL, DL, NVT, InH,
2869+
DAG.getShiftAmountConstant(Amt, NVT, DL));
28672870
}
28682871
return;
28692872
}
28702873

28712874
assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
28722875
if (Amt.uge(VTBits)) {
28732876
Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2874-
DAG.getConstant(NVTBits - 1, DL, ShTy));
2877+
DAG.getShiftAmountConstant(NVTBits - 1, NVT, DL));
28752878
} else if (Amt.ugt(NVTBits)) {
28762879
Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2877-
DAG.getConstant(Amt - NVTBits, DL, ShTy));
2880+
DAG.getShiftAmountConstant(Amt - NVTBits, NVT, DL));
28782881
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2879-
DAG.getConstant(NVTBits - 1, DL, ShTy));
2882+
DAG.getShiftAmountConstant(NVTBits - 1, NVT, DL));
28802883
} else if (Amt == NVTBits) {
28812884
Lo = InH;
28822885
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2883-
DAG.getConstant(NVTBits - 1, DL, ShTy));
2886+
DAG.getShiftAmountConstant(NVTBits - 1, NVT, DL));
28842887
} else {
2885-
Lo = DAG.getNode(ISD::OR, DL, NVT,
2886-
DAG.getNode(ISD::SRL, DL, NVT, InL,
2887-
DAG.getConstant(Amt, DL, ShTy)),
2888-
DAG.getNode(ISD::SHL, DL, NVT, InH,
2889-
DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2890-
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2888+
Lo = DAG.getNode(
2889+
ISD::OR, DL, NVT,
2890+
DAG.getNode(ISD::SRL, DL, NVT, InL,
2891+
DAG.getShiftAmountConstant(Amt, NVT, DL)),
2892+
DAG.getNode(ISD::SHL, DL, NVT, InH,
2893+
DAG.getShiftAmountConstant(-Amt + NVTBits, NVT, DL)));
2894+
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2895+
DAG.getShiftAmountConstant(Amt, NVT, DL));
28912896
}
28922897
}
28932898

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1734,6 +1734,12 @@ SDValue SelectionDAG::getShiftAmountConstant(uint64_t Val, EVT VT,
17341734
return getConstant(Val, DL, ShiftVT);
17351735
}
17361736

1737+
SDValue SelectionDAG::getShiftAmountConstant(const APInt &Val, EVT VT,
1738+
const SDLoc &DL, bool LegalTypes) {
1739+
assert(Val.ult(VT.getScalarSizeInBits()) && "Out of range shift");
1740+
return getShiftAmountConstant(Val.getZExtValue(), VT, DL, LegalTypes);
1741+
}
1742+
17371743
SDValue SelectionDAG::getVectorIdxConstant(uint64_t Val, const SDLoc &DL,
17381744
bool isTarget) {
17391745
return getConstant(Val, DL, TLI->getVectorIdxTy(getDataLayout()), isTarget);

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