[DAG] Add SelectionDAG::getShiftAmountConstant APInt variant #81484
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Asserts that the shift amount is in range and update ExpandShiftByConstant to use getShiftAmountConstant (and legal shift amount types)
|
@llvm/pr-subscribers-llvm-selectiondag Author: Simon Pilgrim (RKSimon) ChangesAsserts that the shift amount is in range and update ExpandShiftByConstant to use getShiftAmountConstant (and legal shift amount types) Full diff: https://github.com/llvm/llvm-project/pull/81484.diff 3 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 886ec0b7940ca8..7bb12d8f065c9d 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -668,6 +668,8 @@ class SelectionDAG {
bool isTarget = false);
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL,
bool LegalTypes = true);
+ SDValue getShiftAmountConstant(const APInt &Val, EVT VT, const SDLoc &DL,
+ bool LegalTypes = true);
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL,
bool isTarget = false);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 39b7e061554141..e73a0921a46f5d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -2824,25 +2824,26 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
EVT NVT = InL.getValueType();
unsigned VTBits = N->getValueType(0).getSizeInBits();
unsigned NVTBits = NVT.getSizeInBits();
- EVT ShTy = N->getOperand(1).getValueType();
if (N->getOpcode() == ISD::SHL) {
if (Amt.uge(VTBits)) {
Lo = Hi = DAG.getConstant(0, DL, NVT);
} else if (Amt.ugt(NVTBits)) {
Lo = DAG.getConstant(0, DL, NVT);
- Hi = DAG.getNode(ISD::SHL, DL,
- NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
+ Hi = DAG.getNode(ISD::SHL, DL, NVT, InL,
+ DAG.getShiftAmountConstant(Amt - NVTBits, NVT, DL));
} else if (Amt == NVTBits) {
Lo = DAG.getConstant(0, DL, NVT);
Hi = InL;
} else {
- Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
- Hi = DAG.getNode(ISD::OR, DL, NVT,
- DAG.getNode(ISD::SHL, DL, NVT, InH,
- DAG.getConstant(Amt, DL, ShTy)),
- DAG.getNode(ISD::SRL, DL, NVT, InL,
- DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
+ Lo = DAG.getNode(ISD::SHL, DL, NVT, InL,
+ DAG.getShiftAmountConstant(Amt, NVT, DL));
+ Hi = DAG.getNode(
+ ISD::OR, DL, NVT,
+ DAG.getNode(ISD::SHL, DL, NVT, InH,
+ DAG.getShiftAmountConstant(Amt, NVT, DL)),
+ DAG.getNode(ISD::SRL, DL, NVT, InL,
+ DAG.getShiftAmountConstant(-Amt + NVTBits, NVT, DL)));
}
return;
}
@@ -2851,19 +2852,21 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
if (Amt.uge(VTBits)) {
Lo = Hi = DAG.getConstant(0, DL, NVT);
} else if (Amt.ugt(NVTBits)) {
- Lo = DAG.getNode(ISD::SRL, DL,
- NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
+ Lo = DAG.getNode(ISD::SRL, DL, NVT, InH,
+ DAG.getShiftAmountConstant(Amt - NVTBits, NVT, DL));
Hi = DAG.getConstant(0, DL, NVT);
} else if (Amt == NVTBits) {
Lo = InH;
Hi = DAG.getConstant(0, DL, NVT);
} else {
- Lo = DAG.getNode(ISD::OR, DL, NVT,
- DAG.getNode(ISD::SRL, DL, NVT, InL,
- DAG.getConstant(Amt, DL, ShTy)),
- DAG.getNode(ISD::SHL, DL, NVT, InH,
- DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
- Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
+ Lo = DAG.getNode(
+ ISD::OR, DL, NVT,
+ DAG.getNode(ISD::SRL, DL, NVT, InL,
+ DAG.getShiftAmountConstant(Amt, NVT, DL)),
+ DAG.getNode(ISD::SHL, DL, NVT, InH,
+ DAG.getShiftAmountConstant(-Amt + NVTBits, NVT, DL)));
+ Hi = DAG.getNode(ISD::SRL, DL, NVT, InH,
+ DAG.getShiftAmountConstant(Amt, NVT, DL));
}
return;
}
@@ -2871,23 +2874,25 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
if (Amt.uge(VTBits)) {
Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
- DAG.getConstant(NVTBits - 1, DL, ShTy));
+ DAG.getShiftAmountConstant(NVTBits - 1, NVT, DL));
} else if (Amt.ugt(NVTBits)) {
Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
- DAG.getConstant(Amt - NVTBits, DL, ShTy));
+ DAG.getShiftAmountConstant(Amt - NVTBits, NVT, DL));
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
- DAG.getConstant(NVTBits - 1, DL, ShTy));
+ DAG.getShiftAmountConstant(NVTBits - 1, NVT, DL));
} else if (Amt == NVTBits) {
Lo = InH;
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
- DAG.getConstant(NVTBits - 1, DL, ShTy));
+ DAG.getShiftAmountConstant(NVTBits - 1, NVT, DL));
} else {
- Lo = DAG.getNode(ISD::OR, DL, NVT,
- DAG.getNode(ISD::SRL, DL, NVT, InL,
- DAG.getConstant(Amt, DL, ShTy)),
- DAG.getNode(ISD::SHL, DL, NVT, InH,
- DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
- Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
+ Lo = DAG.getNode(
+ ISD::OR, DL, NVT,
+ DAG.getNode(ISD::SRL, DL, NVT, InL,
+ DAG.getShiftAmountConstant(Amt, NVT, DL)),
+ DAG.getNode(ISD::SHL, DL, NVT, InH,
+ DAG.getShiftAmountConstant(-Amt + NVTBits, NVT, DL)));
+ Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
+ DAG.getShiftAmountConstant(Amt, NVT, DL));
}
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 55eee780d512c8..421bb516ad242f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1734,6 +1734,12 @@ SDValue SelectionDAG::getShiftAmountConstant(uint64_t Val, EVT VT,
return getConstant(Val, DL, ShiftVT);
}
+SDValue SelectionDAG::getShiftAmountConstant(const APInt &Val, EVT VT,
+ const SDLoc &DL, bool LegalTypes) {
+ assert(Val.ult(VT.getScalarSizeInBits()) && "Out of range shift");
+ return getShiftAmountConstant(Val.getZExtValue(), VT, DL, LegalTypes);
+}
+
SDValue SelectionDAG::getVectorIdxConstant(uint64_t Val, const SDLoc &DL,
bool isTarget) {
return getConstant(Val, DL, TLI->getVectorIdxTy(getDataLayout()), isTarget);
|
arsenm
reviewed
Feb 13, 2024
|
|
||
| if (N->getOpcode() == ISD::SHL) { | ||
| if (Amt.uge(VTBits)) { | ||
| Lo = Hi = DAG.getConstant(0, DL, NVT); | ||
| } else if (Amt.ugt(NVTBits)) { | ||
| Lo = DAG.getConstant(0, DL, NVT); | ||
| Hi = DAG.getNode(ISD::SHL, DL, | ||
| NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy)); |
There was a problem hiding this comment.
I'd generally expect transforms to try to preserve the existing shift operand type?
There was a problem hiding this comment.
The new shifts have a different result type so it seems reasonable to me to update the types of the shift amount to match what the target wants.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Asserts that the shift amount is in range and update ExpandShiftByConstant to use getShiftAmountConstant (and legal shift amount types)