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[DAG] Add SelectionDAG::getShiftAmountConstant APInt variant #81484

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Merged
merged 1 commit into from
Feb 13, 2024
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[DAG] Add SelectionDAG::getShiftAmountConstant APInt variant #81484

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2 changes: 2 additions & 0 deletions llvm/include/llvm/CodeGen/SelectionDAG.h
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Original file line number Diff line number Diff line change
Expand Up @@ -668,6 +668,8 @@ class SelectionDAG {
bool isTarget = false);
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL,
bool LegalTypes = true);
SDValue getShiftAmountConstant(const APInt &Val, EVT VT, const SDLoc &DL,
bool LegalTypes = true);
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL,
bool isTarget = false);

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59 changes: 32 additions & 27 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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Expand Up @@ -2824,25 +2824,26 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
EVT NVT = InL.getValueType();
unsigned VTBits = N->getValueType(0).getSizeInBits();
unsigned NVTBits = NVT.getSizeInBits();
EVT ShTy = N->getOperand(1).getValueType();

if (N->getOpcode() == ISD::SHL) {
if (Amt.uge(VTBits)) {
Lo = Hi = DAG.getConstant(0, DL, NVT);
} else if (Amt.ugt(NVTBits)) {
Lo = DAG.getConstant(0, DL, NVT);
Hi = DAG.getNode(ISD::SHL, DL,
NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
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I'd generally expect transforms to try to preserve the existing shift operand type?

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The new shifts have a different result type so it seems reasonable to me to update the types of the shift amount to match what the target wants.

Hi = DAG.getNode(ISD::SHL, DL, NVT, InL,
DAG.getShiftAmountConstant(Amt - NVTBits, NVT, DL));
} else if (Amt == NVTBits) {
Lo = DAG.getConstant(0, DL, NVT);
Hi = InL;
} else {
Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
Hi = DAG.getNode(ISD::OR, DL, NVT,
DAG.getNode(ISD::SHL, DL, NVT, InH,
DAG.getConstant(Amt, DL, ShTy)),
DAG.getNode(ISD::SRL, DL, NVT, InL,
DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
Lo = DAG.getNode(ISD::SHL, DL, NVT, InL,
DAG.getShiftAmountConstant(Amt, NVT, DL));
Hi = DAG.getNode(
ISD::OR, DL, NVT,
DAG.getNode(ISD::SHL, DL, NVT, InH,
DAG.getShiftAmountConstant(Amt, NVT, DL)),
DAG.getNode(ISD::SRL, DL, NVT, InL,
DAG.getShiftAmountConstant(-Amt + NVTBits, NVT, DL)));
}
return;
}
Expand All @@ -2851,43 +2852,47 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
if (Amt.uge(VTBits)) {
Lo = Hi = DAG.getConstant(0, DL, NVT);
} else if (Amt.ugt(NVTBits)) {
Lo = DAG.getNode(ISD::SRL, DL,
NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
Lo = DAG.getNode(ISD::SRL, DL, NVT, InH,
DAG.getShiftAmountConstant(Amt - NVTBits, NVT, DL));
Hi = DAG.getConstant(0, DL, NVT);
} else if (Amt == NVTBits) {
Lo = InH;
Hi = DAG.getConstant(0, DL, NVT);
} else {
Lo = DAG.getNode(ISD::OR, DL, NVT,
DAG.getNode(ISD::SRL, DL, NVT, InL,
DAG.getConstant(Amt, DL, ShTy)),
DAG.getNode(ISD::SHL, DL, NVT, InH,
DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
Lo = DAG.getNode(
ISD::OR, DL, NVT,
DAG.getNode(ISD::SRL, DL, NVT, InL,
DAG.getShiftAmountConstant(Amt, NVT, DL)),
DAG.getNode(ISD::SHL, DL, NVT, InH,
DAG.getShiftAmountConstant(-Amt + NVTBits, NVT, DL)));
Hi = DAG.getNode(ISD::SRL, DL, NVT, InH,
DAG.getShiftAmountConstant(Amt, NVT, DL));
}
return;
}

assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
if (Amt.uge(VTBits)) {
Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
DAG.getConstant(NVTBits - 1, DL, ShTy));
DAG.getShiftAmountConstant(NVTBits - 1, NVT, DL));
} else if (Amt.ugt(NVTBits)) {
Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
DAG.getConstant(Amt - NVTBits, DL, ShTy));
DAG.getShiftAmountConstant(Amt - NVTBits, NVT, DL));
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
DAG.getConstant(NVTBits - 1, DL, ShTy));
DAG.getShiftAmountConstant(NVTBits - 1, NVT, DL));
} else if (Amt == NVTBits) {
Lo = InH;
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
DAG.getConstant(NVTBits - 1, DL, ShTy));
DAG.getShiftAmountConstant(NVTBits - 1, NVT, DL));
} else {
Lo = DAG.getNode(ISD::OR, DL, NVT,
DAG.getNode(ISD::SRL, DL, NVT, InL,
DAG.getConstant(Amt, DL, ShTy)),
DAG.getNode(ISD::SHL, DL, NVT, InH,
DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
Lo = DAG.getNode(
ISD::OR, DL, NVT,
DAG.getNode(ISD::SRL, DL, NVT, InL,
DAG.getShiftAmountConstant(Amt, NVT, DL)),
DAG.getNode(ISD::SHL, DL, NVT, InH,
DAG.getShiftAmountConstant(-Amt + NVTBits, NVT, DL)));
Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
DAG.getShiftAmountConstant(Amt, NVT, DL));
}
}

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6 changes: 6 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1734,6 +1734,12 @@ SDValue SelectionDAG::getShiftAmountConstant(uint64_t Val, EVT VT,
return getConstant(Val, DL, ShiftVT);
}

SDValue SelectionDAG::getShiftAmountConstant(const APInt &Val, EVT VT,
const SDLoc &DL, bool LegalTypes) {
assert(Val.ult(VT.getScalarSizeInBits()) && "Out of range shift");
return getShiftAmountConstant(Val.getZExtValue(), VT, DL, LegalTypes);
}

SDValue SelectionDAG::getVectorIdxConstant(uint64_t Val, const SDLoc &DL,
bool isTarget) {
return getConstant(Val, DL, TLI->getVectorIdxTy(getDataLayout()), isTarget);
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