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Revert "GlobalISel: Add G_ASSERT_ALIGN hint instruction"
This commit sometimes causes a crash when compiling a vtable thunk. E.g.: clang '--target=aarch64-grtev4-linux-gnu' -xc++ - -c -o /dev/null <<EOF struct a { virtual int f(); }; struct c { virtual int &g() const; }; struct d : a, c { int &g() const; }; int &d::g() const {} EOF Some follow-up commits have been reverted as well: Revert "IR: Make getRetAlign check callee function attributes" Revert "Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFC." Revert "Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFC." This reverts commit 4f414af. This reverts commit a5507d2. This reverts commit 3d2d208. This reverts commit 07ddfa9.
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12 files changed

+19
-371
lines changed

12 files changed

+19
-371
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

Lines changed: 2 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -836,38 +836,17 @@ class MachineIRBuilder {
836836
/// \return a MachineInstrBuilder for the newly created instruction.
837837
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
838838

839-
840-
/// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN
841-
///
842-
/// \return a MachineInstrBuilder for the newly created instruction.
843-
MachineInstrBuilder buildAssertOp(unsigned Opc, const DstOp &Res, const SrcOp &Op,
844-
unsigned Val) {
845-
return buildInstr(Opc, Res, Op).addImm(Val);
846-
}
847-
848839
/// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
849840
///
850841
/// \return a MachineInstrBuilder for the newly created instruction.
851842
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op,
852-
unsigned Size) {
853-
return buildAssertOp(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size);
854-
}
843+
unsigned Size);
855844

856845
/// Build and insert \p Res = G_ASSERT_SEXT Op, Size
857846
///
858847
/// \return a MachineInstrBuilder for the newly created instruction.
859848
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op,
860-
unsigned Size) {
861-
return buildAssertOp(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size);
862-
}
863-
864-
/// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal
865-
///
866-
/// \return a MachineInstrBuilder for the newly created instruction.
867-
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op,
868-
Align AlignVal) {
869-
return buildAssertOp(TargetOpcode::G_ASSERT_ALIGN, Res, Op, AlignVal.value());
870-
}
849+
unsigned Size);
871850

872851
/// Build and insert `Res = G_LOAD Addr, MMO`.
873852
///

‎llvm/include/llvm/IR/InstrTypes.h

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1723,13 +1723,7 @@ class CallBase : public Instruction {
17231723
}
17241724

17251725
/// Extract the alignment of the return value.
1726-
MaybeAlign getRetAlign() const {
1727-
if (auto Align = Attrs.getRetAlignment())
1728-
return Align;
1729-
if (const Function *F = getCalledFunction())
1730-
return F->getAttributes().getRetAlignment();
1731-
return None;
1732-
}
1726+
MaybeAlign getRetAlign() const { return Attrs.getRetAlignment(); }
17331727

17341728
/// Extract the alignment for a call or parameter (0=unknown).
17351729
MaybeAlign getParamAlign(unsigned ArgNo) const {

‎llvm/include/llvm/Support/TargetOpcodes.def

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -228,11 +228,10 @@ HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL)
228228
/// generate code. These instructions only act as optimization hints.
229229
HANDLE_TARGET_OPCODE(G_ASSERT_SEXT)
230230
HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT)
231-
HANDLE_TARGET_OPCODE(G_ASSERT_ALIGN)
232231
HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START,
233232
G_ASSERT_SEXT)
234233
HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END,
235-
G_ASSERT_ALIGN)
234+
G_ASSERT_ZEXT)
236235

237236
/// Generic ADD instruction. This is an integer add.
238237
HANDLE_TARGET_OPCODE(G_ADD)

‎llvm/include/llvm/Target/GenericOpcodes.td

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1434,10 +1434,3 @@ def G_ASSERT_SEXT : GenericInstruction {
14341434
let InOperandList = (ins type0:$src, untyped_imm_0:$sz);
14351435
let hasSideEffects = false;
14361436
}
1437-
1438-
// Asserts that a value has at least the given alignment.
1439-
def G_ASSERT_ALIGN : GenericInstruction {
1440-
let OutOperandList = (outs type0:$dst);
1441-
let InOperandList = (ins type0:$src, untyped_imm_0:$align);
1442-
let hasSideEffects = false;
1443-
}

‎llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Lines changed: 2 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,6 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
8686
CallLoweringInfo Info;
8787
const DataLayout &DL = MIRBuilder.getDataLayout();
8888
MachineFunction &MF = MIRBuilder.getMF();
89-
MachineRegisterInfo &MRI = MF.getRegInfo();
9089
bool CanBeTailCalled = CB.isTailCall() &&
9190
isInTailCallPosition(CB, MF.getTarget()) &&
9291
(MF.getFunction()
@@ -110,7 +109,6 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
110109
CanBeTailCalled = false;
111110
}
112111

113-
114112
// First step is to marshall all the function's parameters into the correct
115113
// physregs and memory locations. Gather the sequence of argument types that
116114
// we'll pass to the assigner function.
@@ -138,39 +136,18 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
138136
else
139137
Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
140138

141-
Register ReturnHintAlignReg;
142-
Align ReturnHintAlign;
143-
144139
Info.OrigRet = ArgInfo{ResRegs, RetTy, 0, ISD::ArgFlagsTy{}};
145-
146-
if (!Info.OrigRet.Ty->isVoidTy()) {
140+
if (!Info.OrigRet.Ty->isVoidTy())
147141
setArgFlags(Info.OrigRet, AttributeList::ReturnIndex, DL, CB);
148142

149-
if (MaybeAlign Alignment = CB.getRetAlign()) {
150-
if (*Alignment > Align(1)) {
151-
ReturnHintAlignReg = MRI.cloneVirtualRegister(ResRegs[0]);
152-
ReturnHintAlign = *Alignment;
153-
std::swap(Info.OrigRet.Regs[0], ReturnHintAlignReg);
154-
}
155-
}
156-
}
157-
158143
Info.CB = &CB;
159144
Info.KnownCallees = CB.getMetadata(LLVMContext::MD_callees);
160145
Info.CallConv = CallConv;
161146
Info.SwiftErrorVReg = SwiftErrorVReg;
162147
Info.IsMustTailCall = CB.isMustTailCall();
163148
Info.IsTailCall = CanBeTailCalled;
164149
Info.IsVarArg = IsVarArg;
165-
if (!lowerCall(MIRBuilder, Info))
166-
return false;
167-
168-
if (ReturnHintAlignReg) {
169-
MIRBuilder.buildAssertAlign(ReturnHintAlignReg, Info.OrigRet.Regs[0],
170-
ReturnHintAlign);
171-
}
172-
173-
return true;
150+
return lowerCall(MIRBuilder, Info);
174151
}
175152

176153
template <typename FuncInfoTy>

‎llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -37,11 +37,6 @@ Align GISelKnownBits::computeKnownAlignment(Register R, unsigned Depth) {
3737
switch (MI->getOpcode()) {
3838
case TargetOpcode::COPY:
3939
return computeKnownAlignment(MI->getOperand(1).getReg(), Depth);
40-
case TargetOpcode::G_ASSERT_ALIGN: {
41-
// TODO: Min with source
42-
int64_t LogAlign = MI->getOperand(2).getImm();
43-
return Align(1ull << LogAlign);
44-
}
4540
case TargetOpcode::G_FRAME_INDEX: {
4641
int FrameIdx = MI->getOperand(1).getIndex();
4742
return MF.getFrameInfo().getObjectAlign(FrameIdx);
@@ -471,18 +466,6 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
471466
Known.Zero.setBitsFrom(SrcBitWidth);
472467
break;
473468
}
474-
case TargetOpcode::G_ASSERT_ALIGN: {
475-
int64_t LogOfAlign = MI.getOperand(2).getImm();
476-
if (LogOfAlign == 0)
477-
break;
478-
479-
// TODO: Should use maximum with source
480-
// If a node is guaranteed to be aligned, set low zero bits accordingly as
481-
// well as clearing one bits.
482-
Known.Zero.setLowBits(LogOfAlign);
483-
Known.One.clearLowBits(LogOfAlign);
484-
break;
485-
}
486469
case TargetOpcode::G_MERGE_VALUES: {
487470
unsigned NumOps = MI.getNumOperands();
488471
unsigned OpSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();

‎llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -282,6 +282,18 @@ MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
282282
return buildInstr(TargetOpcode::COPY, Res, Op);
283283
}
284284

285+
MachineInstrBuilder MachineIRBuilder::buildAssertSExt(const DstOp &Res,
286+
const SrcOp &Op,
287+
unsigned Size) {
288+
return buildInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op).addImm(Size);
289+
}
290+
291+
MachineInstrBuilder MachineIRBuilder::buildAssertZExt(const DstOp &Res,
292+
const SrcOp &Op,
293+
unsigned Size) {
294+
return buildInstr(TargetOpcode::G_ASSERT_ZEXT, Res, Op).addImm(Size);
295+
}
296+
285297
MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
286298
const ConstantInt &Val) {
287299
LLT Ty = Res.getLLTTy(*getMRI());

‎llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -626,8 +626,7 @@ bool RegBankSelect::assignInstr(MachineInstr &MI) {
626626
unsigned Opc = MI.getOpcode();
627627
if (isPreISelGenericOptimizationHint(Opc)) {
628628
assert((Opc == TargetOpcode::G_ASSERT_ZEXT ||
629-
Opc == TargetOpcode::G_ASSERT_SEXT ||
630-
Opc == TargetOpcode::G_ASSERT_ALIGN) &&
629+
Opc == TargetOpcode::G_ASSERT_SEXT) &&
631630
"Unexpected hint opcode!");
632631
// The only correct mapping for these is to always use the source register
633632
// bank.

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3363,8 +3363,6 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
33633363
case ISD::AssertAlign: {
33643364
unsigned LogOfAlign = Log2(cast<AssertAlignSDNode>(Op)->getAlign());
33653365
assert(LogOfAlign != 0);
3366-
3367-
// TODO: Should use maximum with source
33683366
// If a node is guaranteed to be aligned, set low zero bits accordingly as
33693367
// well as clearing one bits.
33703368
Known.Zero.setLowBits(LogOfAlign);

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll

Lines changed: 0 additions & 169 deletions
This file was deleted.

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