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Merge pull request #11297 from kyle-cypress/pr/qspi-dummy-cycles
Differentiate alt and dummy cycles in QSPIF
2 parents 97e11cc + 6bba46e commit 489c30f

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12 files changed

+293
-126
lines changed

12 files changed

+293
-126
lines changed

‎TESTS/mbed_hal/qspi/qspi_test_utils.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -102,10 +102,10 @@ struct Qspi {
102102
#define ADDR_SIZE_24 QSPI_CFG_ADDR_SIZE_24
103103
#define ADDR_SIZE_32 QSPI_CFG_ADDR_SIZE_32
104104

105-
#define ALT_SIZE_8 QSPI_CFG_ALT_SIZE_8
106-
#define ALT_SIZE_16 QSPI_CFG_ALT_SIZE_16
107-
#define ALT_SIZE_24 QSPI_CFG_ALT_SIZE_24
108-
#define ALT_SIZE_32 QSPI_CFG_ALT_SIZE_32
105+
#define ALT_SIZE_8 8u
106+
#define ALT_SIZE_16 16u
107+
#define ALT_SIZE_24 24u
108+
#define ALT_SIZE_32 32u
109109

110110
#define STATUS_REG QSPI_CMD_RDSR
111111
#define CONFIG_REG0 QSPI_CMD_RDCR0

‎components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp

Lines changed: 30 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@ using namespace mbed;
3636
#define UINT64_MAX -1
3737
#endif
3838
#define QSPI_NO_ADDRESS_COMMAND UINT64_MAX
39+
#define QSPI_ALT_DEFAULT_VALUE 0
3940
// Status Register Bits
4041
#define QSPIF_STATUS_BIT_WIP 0x1 //Write In Progress
4142
#define QSPIF_STATUS_BIT_WEL 0x2 // Write Enable Latch
@@ -168,12 +169,12 @@ int QSPIFBlockDevice::init()
168169
_inst_width = QSPI_CFG_BUS_SINGLE;
169170
_address_width = QSPI_CFG_BUS_SINGLE;
170171
_address_size = QSPI_CFG_ADDR_SIZE_24;
172+
_alt_size = 0;
173+
_dummy_cycles = 0;
171174
_data_width = QSPI_CFG_BUS_SINGLE;
172-
_dummy_and_mode_cycles = 0;
173175
_write_register_inst = QSPIF_WRSR;
174176
_read_register_inst = QSPIF_RDSR;
175177

176-
177178
if (QSPI_STATUS_OK != _qspi_set_frequency(_freq)) {
178179
tr_error("QSPI Set Frequency Failed");
179180
status = QSPIF_BD_ERROR_DEVICE_ERROR;
@@ -247,7 +248,7 @@ int QSPIFBlockDevice::init()
247248

248249
// Configure BUS Mode to 1_1_1 for all commands other than Read
249250
_qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
250-
QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
251+
0, QSPI_CFG_BUS_SINGLE, 0);
251252

252253
_is_initialized = true;
253254

@@ -302,17 +303,17 @@ int QSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size)
302303
_mutex.lock();
303304

304305
// Configure Bus for Reading
305-
_qspi_configure_format(_inst_width, _address_width, _address_size, QSPI_CFG_BUS_SINGLE,
306-
QSPI_CFG_ALT_SIZE_8, _data_width, _dummy_and_mode_cycles);
306+
_qspi_configure_format(_inst_width, _address_width, _address_size, _address_width, // Alt width == address width
307+
_alt_size, _data_width, _dummy_cycles);
307308

308309
if (QSPI_STATUS_OK != _qspi_send_read_command(_read_instruction, buffer, addr, size)) {
309310
status = QSPIF_BD_ERROR_DEVICE_ERROR;
310311
tr_error("Read Command failed");
311312
}
312313

313-
// All commands other than Read use default 1-1-1 Bus mode (Program/Erase are constrained by flash memory performance less than that of the bus)
314+
// All commands other than Read use default 1-1-1 Bus mode (Program/Erase are constrained by flash memory performance more than bus performance)
314315
_qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
315-
QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
316+
0, QSPI_CFG_BUS_SINGLE, 0);
316317

317318
_mutex.unlock();
318319
return status;
@@ -718,7 +719,7 @@ int QSPIFBlockDevice::_sfdp_parse_sfdp_headers(uint32_t &basic_table_addr, size_
718719

719720
// Set 1-1-1 bus mode for SFDP header parsing
720721
_qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
721-
QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 8);
722+
0, QSPI_CFG_BUS_SINGLE, 8);
722723

723724
qspi_status_t status = _qspi_send_read_command(QSPIF_SFDP, (char *)sfdp_header, addr /*address*/, data_length);
724725
if (status != QSPI_STATUS_OK) {
@@ -885,7 +886,7 @@ int QSPIFBlockDevice::_sfdp_set_quad_enabled(uint8_t *basic_param_table_ptr)
885886

886887
// Configure BUS Mode to 1_1_1 for all commands other than Read
887888
_qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
888-
QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
889+
0, QSPI_CFG_BUS_SINGLE, 0);
889890

890891
// Read Status Register
891892
if (QSPI_STATUS_OK == _qspi_send_general_command(_read_register_inst, QSPI_NO_ADDRESS_COMMAND, NULL, 0,
@@ -1024,8 +1025,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
10241025
read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE];
10251026
set_quad_enable = true;
10261027
is_qpi_mode = true;
1027-
_dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] >> 5)
1028-
+ (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] & 0x1F);
1028+
_dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] & 0x1F;
1029+
uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] >> 5;
1030+
_alt_size = mode_cycles * 4;
10291031
tr_debug("Read Bus Mode set to 4-4-4, Instruction: 0x%xh", _read_instruction);
10301032
//_inst_width = QSPI_CFG_BUS_QUAD;
10311033
_address_width = QSPI_CFG_BUS_QUAD;
@@ -1038,9 +1040,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
10381040
// Fast Read 1-4-4 Supported
10391041
read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE];
10401042
set_quad_enable = true;
1041-
// dummy cycles + mode cycles = Dummy Cycles
1042-
_dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] >> 5)
1043-
+ (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] & 0x1F);
1043+
_dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] & 0x1F;
1044+
uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] >> 5;
1045+
_alt_size = mode_cycles * 4;
10441046
_address_width = QSPI_CFG_BUS_QUAD;
10451047
_data_width = QSPI_CFG_BUS_QUAD;
10461048
tr_debug("Read Bus Mode set to 1-4-4, Instruction: 0x%xh", _read_instruction);
@@ -1051,8 +1053,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
10511053
// Fast Read 1-1-4 Supported
10521054
read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE];
10531055
set_quad_enable = true;
1054-
_dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] >> 5)
1055-
+ (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] & 0x1F);
1056+
_dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] & 0x1F;
1057+
uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] >> 5;
1058+
_alt_size = mode_cycles;
10561059
_data_width = QSPI_CFG_BUS_QUAD;
10571060
tr_debug("Read Bus Mode set to 1-1-4, Instruction: 0x%xh", _read_instruction);
10581061
break;
@@ -1061,8 +1064,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
10611064
if (examined_byte & 0x01) {
10621065
// Fast Read 2-2-2 Supported
10631066
read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE];
1064-
_dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] >> 5)
1065-
+ (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] & 0x1F);
1067+
_dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] & 0x1F;
1068+
uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] >> 5;
1069+
_alt_size = mode_cycles * 2;
10661070
_address_width = QSPI_CFG_BUS_DUAL;
10671071
_data_width = QSPI_CFG_BUS_DUAL;
10681072
tr_debug("Read Bus Mode set to 2-2-2, Instruction: 0x%xh", _read_instruction);
@@ -1073,8 +1077,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
10731077
if (examined_byte & 0x10) {
10741078
// Fast Read 1-2-2 Supported
10751079
read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE];
1076-
_dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] >> 5)
1077-
+ (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] & 0x1F);
1080+
_dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] & 0x1F;
1081+
uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] >> 5;
1082+
_alt_size = mode_cycles * 2;
10781083
_address_width = QSPI_CFG_BUS_DUAL;
10791084
_data_width = QSPI_CFG_BUS_DUAL;
10801085
tr_debug("Read Bus Mode set to 1-2-2, Instruction: 0x%xh", _read_instruction);
@@ -1083,8 +1088,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
10831088
if (examined_byte & 0x01) {
10841089
// Fast Read 1-1-2 Supported
10851090
read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE];
1086-
_dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] >> 5)
1087-
+ (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] & 0x1F);
1091+
_dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] & 0x1F;
1092+
uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] >> 5;
1093+
_alt_size = mode_cycles;
10881094
_data_width = QSPI_CFG_BUS_DUAL;
10891095
tr_debug("Read Bus Mode set to 1-1-2, Instruction: 0x%xh", _read_instruction);
10901096
break;
@@ -1206,7 +1212,7 @@ int QSPIFBlockDevice::_enable_fast_mdoe()
12061212

12071213
// Configure BUS Mode to 1_1_1 for all commands other than Read
12081214
_qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
1209-
QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
1215+
0, QSPI_CFG_BUS_SINGLE, 0);
12101216

12111217
// Read Status Register
12121218
if (QSPI_STATUS_OK == _qspi_send_general_command(read_conf_register_inst, QSPI_NO_ADDRESS_COMMAND, NULL, 0,
@@ -1306,7 +1312,6 @@ int QSPIFBlockDevice::_utils_iterate_next_largest_erase_type(uint8_t &bitfield,
13061312
tr_error("No erase type was found for current region addr");
13071313
}
13081314
return largest_erase_type;
1309-
13101315
}
13111316

13121317
/***************************************************/
@@ -1323,7 +1328,7 @@ qspi_status_t QSPIFBlockDevice::_qspi_send_read_command(unsigned int read_inst,
13231328
// Send Read command to device driver
13241329
size_t buf_len = size;
13251330

1326-
if (_qspi.read(read_inst, -1, (unsigned int)addr, (char *)buffer, &buf_len) != QSPI_STATUS_OK) {
1331+
if (_qspi.read(read_inst, (_alt_size == 0) ? -1 : QSPI_ALT_DEFAULT_VALUE, (unsigned int)addr, (char *)buffer, &buf_len) != QSPI_STATUS_OK) {
13271332
tr_error("Read failed");
13281333
return QSPI_STATUS_ERROR;
13291334
}

‎components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -357,9 +357,11 @@ class QSPIFBlockDevice : public mbed::BlockDevice {
357357
// Bus speed configuration
358358
qspi_bus_width_t _inst_width; //Bus width for Instruction phase
359359
qspi_bus_width_t _address_width; //Bus width for Address phase
360-
qspi_address_size_t _address_size; // number of bytes for address
360+
qspi_address_size_t _address_size; //Number of bits for address
361+
qspi_alt_size_t _alt_size; //Number of bits for alt
362+
bool _alt_enabled; //Whether alt is enabled
363+
uint8_t _dummy_cycles; //Number of Dummy cycles required by Current Bus Mode
361364
qspi_bus_width_t _data_width; //Bus width for Data phase
362-
int _dummy_and_mode_cycles; // Number of Dummy and Mode Bits required by Current Bus Mode
363365

364366
uint32_t _init_ref_count;
365367
bool _is_initialized;

‎drivers/QSPI.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ class QSPI : private NonCopyable<QSPI> {
106106
* @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
107107
* @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
108108
* @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
109-
* @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ALT_SIZE_8, QSPI_CFG_ALT_SIZE_16, QSPI_CFG_ALT_SIZE_24, QSPI_CFG_ALT_SIZE_32)
109+
* @param alt_size Size in bits used by alt phase (must be a multiple of the number of bus lines indicated in alt_width)
110110
* @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
111111
* @param dummy_cycles Number of dummy clock cycles to be used after alt phase
112112
*

‎drivers/source/QSPI.cpp

Lines changed: 25 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,21 @@ namespace mbed {
2626
QSPI *QSPI::_owner = NULL;
2727
SingletonPtr<PlatformMutex> QSPI::_mutex;
2828

29+
uint8_t convert_bus_width_to_line_count(qspi_bus_width_t width)
30+
{
31+
switch (width) {
32+
case QSPI_CFG_BUS_SINGLE:
33+
return 1;
34+
case QSPI_CFG_BUS_DUAL:
35+
return 2;
36+
case QSPI_CFG_BUS_QUAD:
37+
return 4;
38+
default:
39+
// Unrecognized bus width
40+
return 0;
41+
}
42+
}
43+
2944
QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi()
3045
{
3146
_qspi_io0 = io0;
@@ -38,7 +53,7 @@ QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, Pin
3853
_address_width = QSPI_CFG_BUS_SINGLE;
3954
_address_size = QSPI_CFG_ADDR_SIZE_24;
4055
_alt_width = QSPI_CFG_BUS_SINGLE;
41-
_alt_size = QSPI_CFG_ALT_SIZE_8;
56+
_alt_size = 0;
4257
_data_width = QSPI_CFG_BUS_SINGLE;
4358
_num_dummy_cycles = 0;
4459
_mode = mode;
@@ -52,7 +67,14 @@ QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, Pin
5267

5368
qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width_t address_width, qspi_address_size_t address_size, qspi_bus_width_t alt_width, qspi_alt_size_t alt_size, qspi_bus_width_t data_width, int dummy_cycles)
5469
{
55-
qspi_status_t ret_status = QSPI_STATUS_OK;
70+
// Check that alt_size/alt_width are a valid combination
71+
uint8_t alt_lines = convert_bus_width_to_line_count(alt_width);
72+
if (alt_lines == 0) {
73+
return QSPI_STATUS_ERROR;
74+
} else if (alt_size % alt_lines != 0) {
75+
// Invalid alt size/width combination (alt size is not a multiple of the number of bus lines used to transmit it)
76+
return QSPI_STATUS_ERROR;
77+
}
5678

5779
lock();
5880
_inst_width = inst_width;
@@ -62,10 +84,9 @@ qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width
6284
_alt_size = alt_size;
6385
_data_width = data_width;
6486
_num_dummy_cycles = dummy_cycles;
65-
6687
unlock();
6788

68-
return ret_status;
89+
return QSPI_STATUS_OK;
6990
}
7091

7192
qspi_status_t QSPI::set_frequency(int hz)

‎features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -255,7 +255,7 @@ void test_direct_access_to_device_inject_root()
255255
ret = devkey.device_inject_root_of_trust(key, DEVICE_KEY_16BYTE);
256256
TEST_ASSERT_EQUAL_INT(DEVICEKEY_SUCCESS, ret);
257257

258-
// Now use Direct Access To DeviceKey to retrieve it */
258+
// Now use Direct Access To DeviceKey to retrieve it
259259
uint32_t internal_start_address;
260260
uint32_t internal_rbp_size;
261261
bool is_conf_tdb_internal = false;

‎hal/qspi_api.h

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -60,12 +60,7 @@ typedef enum qspi_address_size {
6060

6161
/** Alternative size in bits
6262
*/
63-
typedef enum qspi_alt_size {
64-
QSPI_CFG_ALT_SIZE_8,
65-
QSPI_CFG_ALT_SIZE_16,
66-
QSPI_CFG_ALT_SIZE_24,
67-
QSPI_CFG_ALT_SIZE_32,
68-
} qspi_alt_size_t;
63+
typedef uint8_t qspi_alt_size_t;
6964

7065
/** QSPI command
7166
*

‎targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -69,21 +69,6 @@ static inline cyhal_qspi_size_t cyhal_qspi_convert_addr_size(qspi_address_size_t
6969
}
7070
}
7171

72-
static inline cyhal_qspi_size_t cyhal_qspi_convert_alt_size(qspi_alt_size_t size)
73-
{
74-
switch (size) {
75-
case QSPI_CFG_ALT_SIZE_8:
76-
return CYHAL_QSPI_CFG_SIZE_8;
77-
case QSPI_CFG_ALT_SIZE_16:
78-
return CYHAL_QSPI_CFG_SIZE_16;
79-
case QSPI_CFG_ALT_SIZE_24:
80-
return CYHAL_QSPI_CFG_SIZE_24;
81-
default: // fallthrough
82-
case QSPI_CFG_ALT_SIZE_32:
83-
return CYHAL_QSPI_CFG_SIZE_32;
84-
}
85-
}
86-
8772
static void cyhal_qspi_convert_command(const qspi_command_t *from, cyhal_qspi_command_t *to)
8873
{
8974
to->instruction.bus_width = cyhal_qspi_convert_width(from->instruction.bus_width);
@@ -94,7 +79,7 @@ static void cyhal_qspi_convert_command(const qspi_command_t *from, cyhal_qspi_co
9479
to->address.value = from->address.value;
9580
to->address.disabled = from->address.disabled;
9681
to->mode_bits.bus_width = cyhal_qspi_convert_width(from->alt.bus_width);
97-
to->mode_bits.size = cyhal_qspi_convert_alt_size(from->alt.size);
82+
to->mode_bits.size = from->alt.size;
9883
to->mode_bits.value = from->alt.value;
9984
to->mode_bits.disabled = from->alt.disabled;
10085
to->dummy_count = from->dummy_count;

‎targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -71,9 +71,12 @@ typedef enum {
7171
} cyhal_qspi_event_t;
7272

7373
#define CYHAL_QSPI_RSLT_ERR_BUS_WIDTH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 0)) /**< Bus width Error. >*/
74-
#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Pin related Error. >*/
75-
#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Data select Error. >*/
76-
#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< QSPI instance related Error. >*/
74+
#define CYHAL_QSPI_RSLT_ERR_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Size Error. >*/
75+
#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Pin related Error. >*/
76+
#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< Data select Error. >*/
77+
#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 4)) /**< QSPI instance related Error. >*/
78+
#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_WIDTH_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 5)) /**< Provided alt size is incompatible with provided alt width. >*/
79+
#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_DUMMY_CYCLES_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 6)) /**< Provided alt size is incompatible with provided number of dummy cycles (due to device-specific restrictions). >*/
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/** @brief QSPI command settings */
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typedef struct cyhal_qspi_command {
@@ -90,7 +93,7 @@ typedef struct cyhal_qspi_command {
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} address;
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struct {
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cyhal_qspi_bus_width_t bus_width; /**< Bus width for mode bits >*/
93-
cyhal_qspi_size_t size; /**< Mode bits size >*/
96+
uint8_t size; /**< Mode bits size >*/
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uint32_t value; /**< Mode bits value >*/
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bool disabled; /**< Mode bits phase skipped if disabled is set to true >*/
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} mode_bits;

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