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Cruz Monrreal
authored
Merge pull request #6638 from adustm/some_disco_boards
[QSPI] Add support for several STM disco boards
2 parents 116e53e + 4d50340 commit e0dcc21

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12 files changed

+137
-9
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12 files changed

+137
-9
lines changed

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,10 @@ typedef enum {
7979
CAN_3 = (int)CAN3_BASE
8080
} CANName;
8181

82+
typedef enum {
83+
QSPI_1 = (int)QSPI_R_BASE,
84+
} QSPIName;
85+
8286
#ifdef __cplusplus
8387
}
8488
#endif

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralPins.c

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -386,3 +386,43 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
386386
{PG_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Pin not available on any connector
387387
{NC, NC, 0}
388388
};
389+
390+
MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
391+
{PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
392+
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0
393+
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1
394+
{PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2
395+
{PC_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3
396+
{PC_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO2
397+
{PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0
398+
{PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1
399+
{PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
400+
{PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
401+
{PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3, N25Q128A13EF840F
402+
{PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2, N25Q128A13EF840F
403+
{PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0
404+
{PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1
405+
{PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2
406+
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3
407+
{PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
408+
{PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
409+
{PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0, N25Q128A13EF840F
410+
{PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1, N25Q128A13EF840F
411+
{PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2
412+
{PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3
413+
{NC, NC, 0}
414+
};
415+
416+
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
417+
{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},
418+
{PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // N25Q128A13EF840F
419+
{PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},
420+
{NC, NC, 0}
421+
};
422+
423+
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
424+
{PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
425+
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_NCS
426+
{PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS, N25Q128A13EF840F
427+
{NC, NC, 0}
428+
};

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,10 @@ struct trng_s {
4444
RNG_HandleTypeDef handle;
4545
};
4646

47+
struct qspi_s {
48+
QSPI_HandleTypeDef handle;
49+
};
50+
4751
#include "common_objects.h"
4852

4953
#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PeripheralPins.c

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -346,21 +346,20 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
346346
};
347347

348348

349-
const PinMap PinMap_QSPI_DATA[] = {
349+
MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
350350
{PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},
351351
{PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},
352-
{PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},
352+
{PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},
353353
{PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},
354-
355354
{NC, NC, 0}
356355
};
357356

358-
const PinMap PinMap_QSPI_SCLK[] = {
357+
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
359358
{PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},
360359
{NC, NC, 0}
361360
};
362361

363-
const PinMap PinMap_QSPI_SSEL[] = {
362+
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
364363
{PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},
365364
{NC, NC, 0}
366365
};

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralNames.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,10 @@ typedef enum {
9393
CAN_2 = (int)CAN2_BASE
9494
} CANName;
9595

96+
typedef enum {
97+
QSPI_1 = (int)QSPI_R_BASE,
98+
} QSPIName;
99+
96100
#ifdef __cplusplus
97101
}
98102
#endif

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PeripheralPins.c

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -207,3 +207,40 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
207207
{PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
208208
{NC, NC, 0}
209209
};
210+
211+
MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
212+
// {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)},
213+
// {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
214+
// {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)},
215+
// {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)},
216+
// {PC_11, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)},
217+
{PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // IO0 connected to N25Q128
218+
{PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // IO1 connected to N25Q128
219+
{PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // IO3 connected to N25Q128
220+
{PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // IO2 connected to N25Q128
221+
// {PE_7, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
222+
// {PE_8, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
223+
// {PE_9, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
224+
// {PE_10, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
225+
{PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // IO3 connected to pin A5
226+
{PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // IO2 connected to pin A4
227+
{PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // IO0 connected to pin A3
228+
{PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // IO1 connected to pin A2
229+
// {PG_9, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)},
230+
// {PG_14, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)},
231+
// {PH_2, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)},
232+
// {PH_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)},
233+
{NC, NC, 0}
234+
};
235+
236+
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
237+
{PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // connected to N25Q128 flash
238+
{NC, NC, 0}
239+
};
240+
241+
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
242+
{PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // connected to N25Q128 flash
243+
// {PC_11, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)},
244+
{NC, NC, 0}
245+
};
246+

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,10 @@ struct trng_s {
5858
RNG_HandleTypeDef handle;
5959
};
6060

61+
struct qspi_s {
62+
QSPI_HandleTypeDef handle;
63+
};
64+
6165
#include "common_objects.h"
6266

6367
#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralNames.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,10 @@ typedef enum {
8383
CAN_1 = (int)CAN1_BASE
8484
} CANName;
8585

86+
typedef enum {
87+
QSPI_1 = (int)QSPI_R_BASE,
88+
} QSPIName;
89+
8690
#ifdef __cplusplus
8791
}
8892
#endif

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralPins.c

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -286,3 +286,29 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
286286
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
287287
{NC, NC, 0}
288288
};
289+
290+
//*** QUADSPI ***
291+
292+
MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
293+
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // IO3 not connected
294+
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // IO2 not connected
295+
{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // IO1 not connected
296+
{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // IO0 not connected
297+
{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // IO0 connected to N25Q128
298+
{PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // IO1 connected to N25Q128
299+
{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // IO2 connected to N25Q128
300+
{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // IO3 connected to N25Q128
301+
{NC, NC, 0}
302+
};
303+
304+
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
305+
// {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
306+
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // connected to N25Q128
307+
{NC, NC, 0}
308+
};
309+
310+
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
311+
// {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
312+
{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // connected to N25Q128
313+
{NC, NC, 0}
314+
};

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,10 @@ struct trng_s {
5858
RNG_HandleTypeDef handle;
5959
};
6060

61+
struct qspi_s {
62+
QSPI_HandleTypeDef handle;
63+
};
64+
6165
#include "common_objects.h"
6266

6367
#ifdef __cplusplus

‎targets/TARGET_STM/qspi_api.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,9 @@
3434
#include "pinmap.h"
3535
#include "PeripheralPins.h"
3636

37-
#define QSPI_FLASH_SIZE_DEFAULT 0x800000
37+
/* Max amount of flash size is 4Gbytes */
38+
/* hence 2^(31+1), then FLASH_SIZE_DEFAULT = 31<<20 */
39+
#define QSPI_FLASH_SIZE_DEFAULT 0x1F00000
3840

3941
void qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTypeDef *st_command)
4042
{

‎targets/targets.json

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1163,7 +1163,7 @@
11631163
},
11641164
"detect_code": ["0743"],
11651165
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
1166-
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
1166+
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH", "QSPI"],
11671167
"release_versions": ["2", "5"],
11681168
"device_name": "STM32F413ZH"
11691169
},
@@ -1846,7 +1846,7 @@
18461846
},
18471847
"detect_code": ["0815"],
18481848
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
1849-
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
1849+
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH", "QSPI"],
18501850
"features": ["LWIP"],
18511851
"release_versions": ["2", "5"],
18521852
"device_name": "STM32F746NG"
@@ -1914,7 +1914,7 @@
19141914
},
19151915
"detect_code": ["0820"],
19161916
"macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
1917-
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
1917+
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH", "QSPI"],
19181918
"release_versions": ["2", "5"],
19191919
"device_name": "STM32L476VG",
19201920
"bootloader_supported": true

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