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Merged
merged 14 commits into from
Apr 12, 2019
Merged

Update CMSIS to 5.5.1 #10366

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c5b5407
cmsis_importer.json: adjust source paths
kjbracey Apr 9, 2019
f967c8b
cmsis_importer: take just Source/os_systick.c
kjbracey Apr 9, 2019
07a2ca3
Move fault handlers to platform directory
kjbracey Apr 10, 2019
00c9005
[CMSIS_5]: Updated to ca812421
kjbracey Apr 10, 2019
4edb719
CMSIS/RTX: Patch RTX4 to preserve osThreadDef compatibility
bulislaw Jul 4, 2017
1aab93a
CMSIS/RTX: Allow overwriting mutex ops for ARMC
bulislaw Oct 18, 2017
b8408bc
CMSIS/RTX: Fix using FALSE/TRUE with preprocesor
bulislaw Apr 30, 2018
58d23af
CMSIS/RTX: Reintroduce arm_math.h
bulislaw May 11, 2018
cd54d2e
CMSIS/RTX: Patch to conditionally compile
Mar 28, 2018
e8f9fae
CMSIS/CORTEX-M: Don't build mbed_tz_context.c in TF-M targets
Jan 3, 2019
9144ecc
CMSIS/RTX: Move Idle and Timer thread stack to bss section.
Dec 13, 2018
d55698e
CMSIS/RTX: Pre-processor defines used for assembly
bulislaw Jul 4, 2017
49928ec
Adjust EVR_RTX disable macros for 5.5.1
kjbracey Apr 10, 2019
020f0e5
Astyle format mbed_fault_handler.[ch]
kjbracey Apr 10, 2019
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32 changes: 24 additions & 8 deletions cmsis/TARGET_CORTEX_A/cmsis_armclang.h
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armclang.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.2
* @date 10. January 2018
* @version V1.1.0
* @date 18. March 2019
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
Expand Down Expand Up @@ -214,7 +214,23 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ (uint8_t)__builtin_clz
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
{
/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
__builtin_clz(0) is undefined behaviour, so handle this case specially.
This guarantees ARM-compatible results if happening to compile on a non-ARM
target, and ensures the compiler doesn't decide to activate any
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
{
return 32U;
}
return __builtin_clz(value);
}

/**
\brief LDR Exclusive (8 bit)
Expand Down Expand Up @@ -375,8 +391,8 @@ __STATIC_FORCEINLINE uint32_t __get_SP_usr()
"MRS %0, cpsr \n"
"CPS #0x1F \n" // no effect in USR mode
"MOV %1, sp \n"
"MSR cpsr_c, %2 \n" // no effect in USR mode
"ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
"MSR cpsr_c, %0 \n" // no effect in USR mode
"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
);
return result;
}
Expand All @@ -391,8 +407,8 @@ __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
"MRS %0, cpsr \n"
"CPS #0x1F \n" // no effect in USR mode
"MOV sp, %1 \n"
"MSR cpsr_c, %2 \n" // no effect in USR mode
"ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
"MSR cpsr_c, %0 \n" // no effect in USR mode
"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
);
}

Expand Down
26 changes: 21 additions & 5 deletions cmsis/TARGET_CORTEX_A/cmsis_gcc.h
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file cmsis_gcc.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.2
* @date 09. April 2018
* @version V1.1.0
* @date 20. December 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Expand Down Expand Up @@ -171,7 +171,7 @@ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
#else
uint32_t result;

__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return result;
#endif
}
Expand Down Expand Up @@ -204,7 +204,7 @@ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
#else
int16_t result;

__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return result;
#endif
}
Expand Down Expand Up @@ -267,7 +267,23 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ (uint8_t)__builtin_clz
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
{
/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
__builtin_clz(0) is undefined behaviour, so handle this case specially.
This guarantees ARM-compatible results if happening to compile on a non-ARM
target, and ensures the compiler doesn't decide to activate any
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
{
return 32U;
}
return __builtin_clz(value);
}

/**
\brief LDR Exclusive (8 bit)
Expand Down
11 changes: 8 additions & 3 deletions cmsis/TARGET_CORTEX_A/cmsis_iccarm.h
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.6
* @date 02. March 2018
* @version V5.0.7
* @date 04. Semptember 2018
******************************************************************************/

//------------------------------------------------------------------------------
Expand Down Expand Up @@ -109,7 +109,12 @@
#endif

#ifndef __RESTRICT
#define __RESTRICT restrict
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif

#ifndef __STATIC_INLINE
Expand Down
13 changes: 6 additions & 7 deletions cmsis/TARGET_CORTEX_A/core_ca.h
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file core_ca.h
* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
* @version V1.0.1
* @date 07. May 2018
* @version V1.0.2
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
* Copyright (c) 2009-2018 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
Expand All @@ -28,13 +28,12 @@
#pragma clang system_header /* treat file as system include file */
#endif

#ifdef __cplusplus
extern "C" {
#endif

#ifndef __CORE_CA_H_GENERIC
#define __CORE_CA_H_GENERIC

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
* CMSIS definitions
Expand Down
8 changes: 6 additions & 2 deletions cmsis/TARGET_CORTEX_M/cmsis_armcc.h
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.4
* @date 10. January 2018
* @version V5.0.5
* @date 14. December 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Expand Down Expand Up @@ -47,6 +47,10 @@
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */

/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif

/* CMSIS compiler specific defines */
#ifndef __ASM
Expand Down
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