Support Nuvoton target NUMAKER_M252KG #11176
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Greentea test: ARMC6 |
Greentea test: GCC_ARM |
Greentea test: IAR |
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@ccli8, thank you for your changes. |
VeijoPesonen
suggested changes
Aug 7, 2019
| @@ -31,13 +31,20 @@ static char buffer[20] = {}; | |||
| static const size_t data_size = 5; | |||
| static size_t actual_size = 0; | |||
| static const size_t buffer_size = 20; | |||
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Having target specific settings inside generic test cases isn't something we can allow. What kind of issue you're trying to solve here?
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NUMAKER_M252KG just has 32KiB SRAM and meet OOM error in the kvstore-static_tests test. So I decrease the number of forked threads from 3 to 2 to reduce memory footprint. I will send another PR to address this issue separately.
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Make modifications:
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@ccli8 Is there any update for this PR? |
No, except for further review request. |
0xc0170
requested changes
Aug 20, 2019
| * @brief M251 Smartcard UART mode (SCUART) driver header file | ||
| * | ||
| * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. | ||
| *****************************************************************************/ |
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Please add the license information (including SPDX identifier) to all StdDriver - already StdDriver for some targets contain the license
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@0xc0170 Fixed by adding BSD-3-Clause license claim to these BSP files
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| #define PRNG_KEY_SIZE (0x20UL) | ||
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| static void trng_get(unsigned char *pConversionData) |
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@ARMmbed/mbed-os-crypto Please review
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Make modifications:
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Please review tools failures in Travis : |
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Make modifications:
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0xc0170
approved these changes
Aug 23, 2019
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CI started |
NU_PINNAME_BIND(...) requires enum PinName to be 32-bit to encode module binding information in it.
USB UART is dedicated to USB COM and so must exclude from FPGA CI testing.
Better IP initialization sequence:
1. Configure IP pins
2. Select IP clock source and then enable it
3. Reset the IP (SYS_ResetModule)
NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if
IP clock enable is before IP reset.
NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then
IP reset.
NOTE3: IP reset at the end of IP initialization sequence can cover unexpected
situation.
Fix logic error on replying NACK at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/ i2c - test single byte read i2c API.
Fix SPI clocks are generated redundantly at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - async mode.
Honor RxIrq/TxIrq to avoid redundant call to UART IRQ handler. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-uart.
In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes. Targets not supporting this feature are listed below: - NUMAKER_PFM_NANO130 - NUMAKER_PFM_NUC472 - NUMAKER_PFM_M453
Without free-up of peripheral pins, peripheral pins of the same peripheral may share by multiple ports after port iteration, and this peripheral may fail with pin interference.
Reasons to remove TRNG support: 1. M252 just has 32KiB SRAM and cannot afford mbedtls application. 2. Implementing TRNG HAL with PRNG H/W has security concern.
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@cyliangtw It is feasible, but it is harder than it looks, there are many pitfalls and therefore the entropy content needs to be estimated very carefully and conservatively. (For example f the ADC is connected to a sensor, then it is easy to manipulate, if it is not, the entropy content drops drastically when connected to a power source. Either way it usually picks up a lot of noise from the digital components, which part again can usually be manipulated.) The plan you mentioned seems to use the HW PRBG as a conditioning component. I don't know what algorithm that means, but it is best to make sure that it is one of the approved algorithms (3.1.5.1.1 in NIST SP 800-90B). Although the resulting solution does not have to be NIST certified/validated in order for us to accept, it still has to be NIST SP 800-90B compliant (ie. self validated). This fact needs to be documented and the entropy estimates have to be clearly stated. |
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@yanesca In our chip, we have one internal voltage through MCU internal LDO solution, so it could avoid the pitfalls you mentioned. We will create another 2 PRs near future, one is for HW TRNG, the other is for this RNG implementation and we could continue review/discuss in that PR. |
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Removed |
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Update? |
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CI started |
Test run: SUCCESSSummary: 11 of 11 test jobs passed |
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Description
This PR adds Nuvoton's target NUMAKER_M252KG. NUMAKER_M252KG is Cortex-M23 based without TrustZone. It supports the following toolchains:
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