OLIMEX_STM32E407_F407ZG: Added new target platform

features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_OLIMEX_STM32E407_F407ZG/stm32f4_eth_conf.c

@@ -0,0 +1,60 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "stm32f4xx_hal.h"
+
+void _eth_config_mac(ETH_HandleTypeDef *heth)
+{
+    ETH_MACInitTypeDef macconf = {
+        .Watchdog = ETH_WATCHDOG_ENABLE,
+        .Jabber = ETH_JABBER_ENABLE,
+        .InterFrameGap = ETH_INTERFRAMEGAP_96BIT,
+        .CarrierSense = ETH_CARRIERSENCE_ENABLE,
+        .ReceiveOwn = ETH_RECEIVEOWN_ENABLE,
+        .LoopbackMode = ETH_LOOPBACKMODE_DISABLE,
+        .ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE,
+        .RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE,
+        .AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE,
+        .BackOffLimit = ETH_BACKOFFLIMIT_10,
+        .DeferralCheck = ETH_DEFFERRALCHECK_DISABLE,
+        .ReceiveAll = ETH_RECEIVEAll_DISABLE,
+        .SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE,
+        .PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL,
+        .BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE,
+        .DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL,
+        .PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE,
+        .MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_NONE, // Disable multicast filter
+        .UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT,
+        .HashTableHigh = 0x0U,
+        .HashTableLow = 0x0U,
+        .PauseTime = 0x0U,
+        .ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE,
+        .PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4,
+        .UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE,
+        .ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE,
+        .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE,
+        .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT,
+        .VLANTagIdentifier = 0x0U,
+    };
+
+    if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) {
+        macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
+    } else {
+        macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
+    }
+
+    (void) HAL_ETH_ConfigMAC(heth, &macconf);
+}

features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_OLIMEX_STM32E407_F407ZG/stm32f4_eth_init.c

@@ -0,0 +1,114 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
+
+#include "stm32f4xx_hal.h"
+
+/**
+ * Override HAL Eth Init function
+ */
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
+{
+    GPIO_InitTypeDef GPIO_InitStructure;
+    if (heth->Instance == ETH) {
+
+        /* Enable GPIOs clocks */
+        __HAL_RCC_GPIOA_CLK_ENABLE();
+        __HAL_RCC_GPIOB_CLK_ENABLE();
+        __HAL_RCC_GPIOC_CLK_ENABLE();
+        __HAL_RCC_GPIOG_CLK_ENABLE();
+
+        /** ETH GPIO Configuration
+          RMII_REF_CLK ----------------------> PA1
+          RMII_MDIO -------------------------> PA2
+          RMII_MDC --------------------------> PC1
+          RMII_MII_CRS_DV -------------------> PA7
+          RMII_MII_RXD0 ---------------------> PC4
+          RMII_MII_RXD1 ---------------------> PC5
+          RMII_MII_RXER ---------------------> none
+          RMII_MII_TX_EN --------------------> PG11
+          RMII_MII_TXD0 ---------------------> PG13
+          RMII_MII_TXD1 ---------------------> PG14
+         */
+        /* Configure PA1, PA2 and PA7 */
+        GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
+        GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
+        GPIO_InitStructure.Pull = GPIO_NOPULL;
+        GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
+        GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
+        HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+        /* Configure PC1, PC4 and PC5 */
+        GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
+        HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+        /* Configure PG2, PG11 and PG13 */
+        GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
+        HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+        /* Enable the Ethernet global Interrupt */
+        HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
+        HAL_NVIC_EnableIRQ(ETH_IRQn);
+
+        /* Enable ETHERNET clock  */
+        __HAL_RCC_ETH_CLK_ENABLE();
+    }
+}
+
+/**
+ * Override HAL Eth DeInit function
+ */
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
+{
+    if (heth->Instance == ETH) {
+        /* Peripheral clock disable */
+        __HAL_RCC_ETH_CLK_DISABLE();
+
+        /** ETH GPIO Configuration
+        RMII_REF_CLK ----------------------> PA1
+        RMII_MDIO -------------------------> PA2
+        RMII_MDC --------------------------> PC1
+        RMII_MII_CRS_DV -------------------> PA7
+        RMII_MII_RXD0 ---------------------> PC4
+        RMII_MII_RXD1 ---------------------> PC5
+        RMII_MII_RXER ---------------------> none
+        RMII_MII_TX_EN --------------------> PG11
+        RMII_MII_TXD0 ---------------------> PG13
+        RMII_MII_TXD1 ---------------------> PG14
+         */
+        HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
+        HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
+        HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14);
+
+        /* Disable the Ethernet global Interrupt */
+        NVIC_DisableIRQ(ETH_IRQn);
+    }
+}
+
+#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_OLIMEX_STM32E407_F407ZG/PeripheralNames.h

@@ -0,0 +1,96 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int)ADC2_BASE,
+    ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+    DAC_0 = 0,
+    DAC_1
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE,
+    UART_6 = (int)USART6_BASE,
+} UARTName;
+
+#define DEVICE_SPI_COUNT 3
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_9  = (int)TIM9_BASE,
+    PWM_10 = (int)TIM10_BASE,
+    PWM_11 = (int)TIM11_BASE,
+    PWM_12 = (int)TIM12_BASE,
+    PWM_13 = (int)TIM13_BASE,
+    PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE,
+    CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif