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MIMXRT1050: Update for deep sleep latency #12364

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Feb 7, 2020
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Original file line number Diff line number Diff line change
Expand Up @@ -132,32 +132,14 @@ void CLOCK_SET_DIV(clock_div_t divider, uint32_t value)

void ClockSelectXtalOsc(void)
{
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Wait CCM operation finishes */
CLOCK_CCM_HANDSHAKE_WAIT();
/* Take some delay */
SDK_DelayAtLeastUs(40);
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Turn off XTAL-OSC detector */
CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK;
/* Power Down internal RC. */
CLOCK_DeinitRcOsc24M();
}

void ClockSelectRcOsc(void)
{
/* Enable internal RC. */
XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK;
/* Wait CCM operation finishes */
CLOCK_CCM_HANDSHAKE_WAIT();
/* Take some delay */
SDK_DelayAtLeastUs(4000);
/* Switch clock source to internal RC. */
XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK;
/* Disable XTAL 24MHz clock source. */
CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK;
}

void LPM_SetRunModeConfig(void)
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2 changes: 1 addition & 1 deletion targets/targets.json
Original file line number Diff line number Diff line change
Expand Up @@ -2865,7 +2865,7 @@
],
"device_name": "MIMXRT1052",
"overrides": {
"deep-sleep-latency": 5,
"deep-sleep-latency": 10,
"network-default-interface-type": "ETHERNET"
}
},
Expand Down