Add ARMC6 feature to EV_COG_AD4050LZ and EV_COG_AD3029LZ #5541
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I'm going to explain why these tests are superfluous because I don't like removing tests. The asserts were all asserting something that does not need to be true: that the toolchain's `name` attribute matched it's key in the `TOOLCHIAN_CLASSES` dictionary. With that out of the way, the `test_instantiation` test did not assert anything, and is therefore not a test.
Arm compiler 6 optimized way too well, and adding 2 more nops did the trick
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| #define TRNG_PRESCALER 2 | |||
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| /* RNG Device memory */ | |||
| static uint8_t RngDevMem[ADI_RNG_MEMORY_SIZE]; | |||
| static uint32_t RngDevMem[(ADI_RNG_MEMORY_SIZE + 3)/4]; | |||
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This does not seem to be related to armc6, shall be separate commit
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The default alignment is set to 1 byte by ARMC6. uint32_t gurantee 4 byte alignment.
static uint8_t RngDevMem[ADI_RNG_MEMORY_SIZE]; exactly causes ARMC6 greentea tests fail in test case mbed-os-tests-mbedtls-selftest.
static uint32_t RngDevMem[(ADI_RNG_MEMORY_SIZE+3)/4]; pass in test case mbed-os-tests-mbedtls-selftest for both ARMC6 and ARMC5.
The code is meant be compatible for both ARMC6 and ARMC5.
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Thanks for the explanation, please use commit msg to provide more detailed description for changes. If you can, I would ammend the commit and add there details for changes.
targets/targets.json
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| }, | |||
| "EV_COG_AD4050LZ": { | |||
| "inherits": ["Target"], | |||
| "core": "Cortex-M4", | |||
| "core": "Cortex-M4F", | |||
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This does not seem to be related to armc6, shall be separate commit
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Cortex-M4 for ARMC6 result in all SYNC_FAILED in all greentea tests.
Cortex-M4F for ARMC5 and ARMC6 pass all greentea tests.
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Cortex-M4 is also an issue to ADuCM4050 IAR exporter because Embedded Workbench is pre-configured by ADuCM4050 Board Support Package to assume that ADuCM4050's FPU is present and enabled for IDE. The inconsistent FPU settings in IAR IDE will cause Bus fault Exception eventually.
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In case this is backward compatible, it could go to master. However, I would like to have this tested with ARMC6 (if we dont do it, it can block later armc6 patches). To enable that, this would needs to be redirected for armc6 branch. Can you please redirect this PR to armc6? Here is the branch - https://github.com/ARMmbed/mbed-os/tree/feature-armc6 If there is fix like that fpu in targets.json file (any bugfix that should go to master, its not armc6 only related) should be sent as separate PR to master, and we can armc6 branch update to the master to have this fix propagated as well there. This way master would be updated with bugfixes for these targets, and branch armc6 with bugfixes to enable armc6 for these targets. Do you have any other suggestions? |
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Initial commit of mbed TLS hardware acceleration drivers for Silicon Labs parts
* Use _C flags at compile time in SHA to avoid compiling in unconfigured features * Don't define ECP_SHORTWEIERSTRASS since it is part of the application's configuration
This implementation returns the number of available (stored) transactions in the buffer
- Removed unneeded code from i2c and serial modules.
…ady; - Added a configuration call in trng_init to make sure the TRNG buffering mode is disabled, so only 8-bit bytes are returned; - Moved the TRNG device handle into the trng_t structure; - Fixed some formatting errors in the adc driver.
- Added curly brackets to single line conditions in gpio_qpi.c and gpio_irq_api.c; - Changed rx and tx buffers in serial module as local variables; - Minor i2c & spi updates for github pull request; - Added function definition for spi_master_block_write.
…ter_block_write; - Some clean up in serai_api.
…se LowPowerTimer, LowPowerTimeout and LowPowerTicker instead of Timer/Timeout/Ticker. This way, on SiLabs boards the low power sleep states will be used when using event queue.
This macro yields a string literal of the enclosing function name.
Turn the compile time error issued when a NonCopyable resource is copied into a compile time and runtime warning. If the application is compiled with the debug profile the compile time error remains. The compile time error can be enforced by setting the library option force-non-copyable-error to true.
Fixed issues raised from ARM PR review and removed the unsupported platform. - Fixed an issue where the TRNG is read even though it may not be ready; - Added configuration to ensure the buffering mode is disabled so only 8-bit bytes are generated; - Moved the TRNG device handle into the trng_t structure. Removed undefined spi slave related functions. - Added error checking for trng_get_bytes function; - Added curly brackets to single line conditions for some files; - Changed rx and tx buffers in serial module as local variables; - Removed some unused code and some minor formatting corrections; - Minor i2c & spi updates for github pull request; - Added function definition for spi_master_block_write. Added default delay and sample times for the ADC during initialization. - Added code to clear stack variable in trng_get_bytes upon exiting the function; - Remove lp ticker functionality as the timer hardware does not satisfy lp timer requirements. Added a check for the STUCK bit before reading the RNG data register to ensure there are no hardware faults. - Removed .mbedignore to work around some exporter issues; - Added #includes to some of the driver data C files for them to build on their own.
Re-casting with tmp the uint8_t* pData pointer to uint16_t* brings a memory corruption and typically can corrupt the size parameter. This is fixed with this commit. STM32 Internal ticket reference : 39116
Fix the circular linked list handling in ConditionVariable and add a test to validate the linked list implementation.
The index field of FATFS_DIR does not encapsulate all the context required to reposition the directory traversal. ChaN provides f_rewinddir() but no directory seek, so rewind if necessary then step through until the desired index is reached.
Compatible code for ARM 5 and ARM 6 while default alignment settings differ.
Instance memory containing memory pointers must be 4 byte aligned for all compilers regardless compilers' settings or configurations. uint32_t is recommended to replace uint8_t for instance memory declaration because uint32_t guarantee 4 byte alignment.
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li-ho:ev_cog_armc6 is rebased and |
Description
Add ARMC6 feature to EV_COG_AD4050LZ and EV_COG_AD3029LZ
Status
READY
Migrations
NO
Related PRs
#5144
#5137