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FUTURE_SEQUANA_PSA: fixed deep sleep mode #9678

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Merged
merged 1 commit into from
Feb 13, 2019
Merged

FUTURE_SEQUANA_PSA: fixed deep sleep mode #9678

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9 changes: 7 additions & 2 deletions targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_CY8C63XX/device.h
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Original file line number Diff line number Diff line change
Expand Up @@ -67,9 +67,13 @@
* multiplexer. This requires that we define which of the 32 NVIC channels is used
* by which interrupt. This is done here.
*/
#define CY_M0_CORE_IRQ_CHANNEL_US_TICKER ((IRQn_Type)0)
#define CY_M0_CORE_IRQ_CHANNEL_LP_TICKER ((IRQn_Type)0)
#define CY_M0_CORE_IRQ_CHANNEL_IPC_SYS ((IRQn_Type)1)
#define CY_M0_CORE_IRQ_CHANNEL_IPC_USR ((IRQn_Type)2)
#define CY_M0_CORE_IRQ_CHANNEL_PSA_MAILBOX ((IRQn_Type)3)
#define CY_M0_CORE_IRQ_CHANNEL_SERIAL ((IRQn_Type)4)
#define CY_M0_CORE_IRQ_CHANNEL_BLE ((IRQn_Type)3)
#define CY_M0_CORE_IRQ_CHANNEL_BLE ((IRQn_Type)7)
#define CY_M0_CORE_IRQ_CHANNEL_US_TICKER ((IRQn_Type)8)

/** Identifiers used in allocation of NVIC channels.
*/
Expand All @@ -78,4 +82,5 @@
#define CY_BLE_IRQN_ID (0x300)
#define CY_GPIO_IRQN_ID (0x400)
#define CY_LP_TICKER_IRQN_ID (0x500)
#define CY_PSA_MAILBOX_IRQN_ID (0x600)
#endif
10 changes: 7 additions & 3 deletions targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/TARGET_FUTURE_SEQUANA_M0_PSA/spm_init_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -20,12 +20,13 @@

#include "spm_api.h"

#include "cmsis.h"
#include "device.h"
#include "cyip_ipc.h"
#include "cy_ipc_drv.h"
#include "cy_syslib.h"
#include "cy_sysint.h"

#include "psoc6_utils.h"
#include "mbed_error.h"


/* ------------------------------------ Definitions ---------------------------------- */
Expand Down Expand Up @@ -65,9 +66,12 @@ void mailbox_init(void)

// Configure interrupts ISR / MUX and priority
cy_stc_sysint_t ipc_intr_Config;
ipc_intr_Config.intrSrc = (IRQn_Type)NvicMux3_IRQn; // Can be any Mux we choose
ipc_intr_Config.intrSrc = CY_M0_CORE_IRQ_CHANNEL_PSA_MAILBOX;
ipc_intr_Config.cm0pSrc = (cy_en_intr_t)cpuss_interrupts_ipc_0_IRQn + SPM_IPC_NOTIFY_CM0P_INTR; // Must match the interrupt we trigger using NOTIFY on CM4
ipc_intr_Config.intrPriority = 1;
if (cy_m0_nvic_reserve_channel(CY_M0_CORE_IRQ_CHANNEL_PSA_MAILBOX, CY_PSA_MAILBOX_IRQN_ID) == (IRQn_Type)(-1)) {
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-1 is oddly specific. What does the magic number map to?

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It refers to targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/psoc6_utils.h:

 *
 * \param channel IRQn_Type     Channel to be reserved.
 * \param allocation_id uint32_t    Identifier.
 * \return  IRQ channel allocated or (-1) if no free channel is available.
 *
 */
IRQn_Type cy_m0_nvic_reserve_channel(IRQn_Type channel, uint32_t allocation_id);

Yeah, it's sloppy. But fixing this requires a global HAL implementation change, that I would rather prepare as a separate PR.

error("PSA SPM Mailbox NVIC channel reservation conflict.");
}
(void)Cy_SysInt_Init(&ipc_intr_Config, ipc_interrupt_handler);

// Set specific NOTIFY interrupt mask only.
Expand Down
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