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Digital: Adds Logic and defines 9 logic levels, StdULogicVector, and StdLogicVector #144

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Merged
merged 13 commits into from
Feb 17, 2023

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ven-k
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@ven-k ven-k commented Jan 22, 2023

First in series of PRs to implement the entire IEEE.Std_logic_1164 in Julia

  • Adds Logic and its 9 levels
  • Accordingly refactors AndTable, OrTable, NotTable, XorTable
  • Accordingly refactors _and, _or, _not, _xor
  • Adds StdULogicVector and few predefined vectors and StdLogicVector
  • Adds relevant tests

This PR will be followed up to add things like:

  • Resolution table
  • Inter-conversions from one range of logic-levels to other range
  • Digital sources, clocks
  • High level DiscreteSystems of gates
  • And then revival of Adders, En(/De)coders, (De)Muxes

@ven-k ven-k force-pushed the vk/logictables branch 2 times, most recently from c320139 to 2c6ee42 Compare January 27, 2023 18:23
@ven-k ven-k marked this pull request as ready for review January 27, 2023 18:24
@ven-k ven-k requested a review from baggepinnen January 27, 2023 18:24
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codecov bot commented Jan 27, 2023

Codecov Report

Merging #144 (de1fc3d) into main (56e4bd9) will increase coverage by 2.21%.
The diff coverage is 72.82%.

@@            Coverage Diff             @@
##             main     #144      +/-   ##
==========================================
+ Coverage   67.35%   69.57%   +2.21%     
==========================================
  Files          33       35       +2     
  Lines        1498     1558      +60     
==========================================
+ Hits         1009     1084      +75     
+ Misses        489      474      -15     
Impacted Files Coverage Δ
src/Electrical/Digital/logic.jl 46.87% <46.87%> (ø)
src/Electrical/Digital/tables.jl 84.90% <82.97%> (+84.90%) ⬆️
src/Electrical/Digital/logic_vectors.jl 100.00% <100.00%> (ø)
src/Blocks/analysis_points.jl 83.69% <0.00%> (+0.42%) ⬆️
src/Thermal/HeatTransfer/ideal_components.jl 100.00% <0.00%> (+2.04%) ⬆️

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@ven-k ven-k force-pushed the vk/logictables branch 2 times, most recently from 3872762 to 41e76d2 Compare January 29, 2023 16:30
@ven-k ven-k requested a review from baggepinnen February 5, 2023 18:40
i::Int)
getindex(s.logic, i)
end
function Base.getindex(s::LogicVector, i1::Int, i2::Int,
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Why do we call it a vector if it can be multidimensional?

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@ven-k ven-k Feb 9, 2023

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To remain consistent with std_logic_vector and std_ulogic_vector are the names used in IEEE Std_logic_1164.
Although its mostly used in vector form, it can be a matrix as well.


struct StdULogicVector{N} <: AbstractArray{Logic, N}
logic::Array{Logic}
level::Array{Int}
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Why do we need to store level at all if it can be trivially computed from logic?

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As we use level for indexing, having level would be easier to access the logic tables

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Should we have a logic table so that it takes Logic indices, then?

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This point is still not addressed. We need LogicTable{N} <: AbstractArray{Logic, N} such that we can index into it using Logic indices, so we don't even need to store level.

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This seemed like the simplest approach to index the values.
I see the point in a LogicTable type. Will implement that.

end
end

const LogicVector = Union{StdULogicVector, StdLogicVector}
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What are they used for?

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StdULogicVector, StdLogicVector are part the Std_logic_1164.
LogicVector is only for convenience while writing dispatches.

- refactor logic gate tables with LogicTable
@ven-k ven-k requested a review from YingboMa February 14, 2023 11:27
@YingboMa YingboMa merged commit a4619b9 into SciML:main Feb 17, 2023
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3 participants