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[SYCL][FPGA] Add defaults for streaming and register_map fpga_kernel_properties, fix RegisterMap sycl-post-link #10406

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Merged
merged 4 commits into from
Jul 25, 2023
Merged

[SYCL][FPGA] Add defaults for streaming and register_map fpga_kernel_properties, fix RegisterMap sycl-post-link #10406

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f6b36b4
add defaults for fpga_kernel_properties, refactor to match SPIRV spec.
bowenxue-intel Jul 14, 2023
d7d9192
clang-format and fix spelling error
bowenxue-intel Jul 14, 2023
be9ec78
small fix for incorrect template var name
bowenxue-intel Jul 15, 2023
0d0ab3f
Merge remote-tracking branch 'intel/sycl' into fpga_kernel_properties
bowenxue-intel Jul 18, 2023
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32 changes: 18 additions & 14 deletions llvm/lib/SYCLLowerIR/CompileTimePropertiesPass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -251,25 +251,29 @@ attributeToExecModeMetadata(const Attribute &Attr, Function &F) {
MDNode::get(Ctx, MD));
}

auto getIpInterface = [](const char *Name, LLVMContext &Ctx,
const Attribute &Attr) {
if (AttrKindStr == "sycl-streaming-interface") {
// generate either:
// !N = !{!"<name>"} or
// !N = !{!"<name>", !"stall_free_return"}
// !N = !{!"streaming"} or
// !N = !{!"streaming", !"stall_free_return"}
SmallVector<Metadata *, 2> MD;
MD.push_back(MDString::get(Ctx, Name));
MD.push_back(MDString::get(Ctx, "streaming"));
if (getAttributeAsInteger<uint32_t>(Attr))
MD.push_back(MDString::get(Ctx, "stall_free_return"));
return MDNode::get(Ctx, MD);
};

if (AttrKindStr == "sycl-streaming-interface")
return std::pair<std::string, MDNode *>(
"ip_interface", getIpInterface("streaming", Ctx, Attr));
return std::pair<std::string, MDNode *>("ip_interface",
MDNode::get(Ctx, MD));
}

if (AttrKindStr == "sycl-register-map-interface")
if (AttrKindStr == "sycl-register-map-interface") {
// generate either:
// !N = !{!"csr"} or
// !N = !{!"csr", !"wait_for_done_write"}
SmallVector<Metadata *, 2> MD;
MD.push_back(MDString::get(Ctx, "csr"));
if (getAttributeAsInteger<uint32_t>(Attr))
MD.push_back(MDString::get(Ctx, "wait_for_done_write"));
return std::pair<std::string, MDNode *>("ip_interface",
getIpInterface("csr", Ctx, Attr));
MDNode::get(Ctx, MD));
}

if ((AttrKindStr == SYCL_REGISTER_ALLOC_MODE_ATTR ||
AttrKindStr == SYCL_GRF_SIZE_ATTR) &&
Expand Down Expand Up @@ -372,7 +376,7 @@ PreservedAnalyses CompileTimePropertiesPass::run(Module &M,
if (isHostPipeVariable(GV)) {
auto VarName = getGlobalVariableUniqueId(GV);
MDOps.push_back(buildSpirvDecorMetadata(Ctx, SPIRV_HOST_ACCESS_DECOR,
SPIRV_HOST_ACCESS_DEFAULT_VALUE,
SPIRV_HOST_ACCESS_DEFAULT_VALUE,
VarName));
}

Expand Down
10 changes: 5 additions & 5 deletions llvm/test/SYCLLowerIR/CompileTimePropertiesPass/kernel-attributes/register-map-interface.ll
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Original file line number Diff line number Diff line change
@@ -1,16 +1,16 @@
; Check conversion of sycl-register-map-interface attribute
; RUN: opt -passes="compile-time-properties" %s -S -o - | FileCheck %s --check-prefix CHECK-IR

; CHECK-IR-DAG: @pStreaming() #0 {{.*}}!ip_interface [[REGISTER_MAP:![0-9]+]] {
; CHECK-IR-DAG: @pRegisterMap() #0 {{.*}}!ip_interface [[REGISTER_MAP:![0-9]+]] {
; Function Attrs: convergent norecurse
define weak_odr dso_local spir_kernel void @pStreaming() #0 {
define weak_odr dso_local spir_kernel void @pRegisterMap() #0 {
entry:
ret void
}

; CHECK-IR-DAG: @pStallFreeStreaming() #1 {{.*}}!ip_interface [[STALL_FREE_REGISTER_MAP:![0-9]+]] {
; CHECK-IR-DAG: @pWaitRegisterMap() #1 {{.*}}!ip_interface [[WAIT_REGISTER_MAP:![0-9]+]] {
; Function Attrs: convergent norecurse
define weak_odr dso_local spir_kernel void @pStallFreeStreaming() #1 {
define weak_odr dso_local spir_kernel void @pWaitRegisterMap() #1 {
entry:
ret void
}
Expand All @@ -31,4 +31,4 @@ attributes #1 = { convergent norecurse "frame-pointer"="all" "sycl-register-map-

; Confirm the decorations for the functions
; CHECK-IR-DAG: [[REGISTER_MAP]] = !{!"csr"}
; CHECK-IR-DAG: [[STALL_FREE_REGISTER_MAP]] = !{!"csr", !"stall_free_return"}
; CHECK-IR-DAG: [[WAIT_REGISTER_MAP]] = !{!"csr", !"wait_for_done_write"}
14 changes: 8 additions & 6 deletions sycl/include/sycl/ext/intel/experimental/fpga_kernel_properties.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,8 @@ enum class streaming_interface_options_enum : std::uint16_t {
};

enum class register_map_interface_options_enum : std::uint16_t {
do_not_wait_for_done_write,
wait_for_done_write,
do_not_wait_for_done_write
};

struct streaming_interface_key {
Expand All @@ -49,7 +49,8 @@ struct pipelined_key {
std::integral_constant<int, pipeline_directive_or_initiation_interval>>;
};

template <streaming_interface_options_enum option>
template <streaming_interface_options_enum option =
streaming_interface_options_enum::accept_downstream_stall>
inline constexpr streaming_interface_key::value_t<option> streaming_interface;

inline constexpr streaming_interface_key::value_t<
Expand All @@ -60,7 +61,8 @@ inline constexpr streaming_interface_key::value_t<
streaming_interface_options_enum::remove_downstream_stall>
streaming_interface_remove_downstream_stall;

template <register_map_interface_options_enum option>
template <register_map_interface_options_enum option =
register_map_interface_options_enum::do_not_wait_for_done_write>
inline constexpr register_map_interface_key::value_t<option>
register_map_interface;

Expand Down Expand Up @@ -128,12 +130,12 @@ template <>
struct IsCompileTimeProperty<intel::experimental::pipelined_key>
: std::true_type {};

template <intel::experimental::streaming_interface_options_enum Stall>
template <intel::experimental::streaming_interface_options_enum Stall_Free>
struct PropertyMetaInfo<
intel::experimental::streaming_interface_key::value_t<Stall>> {
intel::experimental::streaming_interface_key::value_t<Stall_Free>> {
static constexpr const char *name = "sycl-streaming-interface";
static constexpr intel::experimental::streaming_interface_options_enum value =
Stall;
Stall_Free;
};
template <intel::experimental::register_map_interface_options_enum Wait>
struct PropertyMetaInfo<
Expand Down