Skip to content

[Driver][SYCL][FPGA] Do not generate host dependency files by default #1918

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Jun 22, 2020
Merged

[Driver][SYCL][FPGA] Do not generate host dependency files by default #1918

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
6a9cc5e
[Driver][SYCL][FPGA] Do not generate host dependency files by default
mdtoguchi Jun 18, 2020
f2985a4
[NFC] Update test to check for -MT addition which is required for dep…
mdtoguchi Jun 22, 2020
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 1 addition & 2 deletions clang/lib/Driver/Driver.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -407,9 +407,8 @@ DerivedArgList *Driver::TranslateInputArgs(const InputArgList &Args) const {
if (Args.hasFlag(options::OPT_miamcu, options::OPT_mno_iamcu, false))
DAL->AddFlagArg(0, Opts.getOption(options::OPT_static));

// Use of -fintelfpga implies -g and -MMD
// Use of -fintelfpga implies -g
if (Args.hasArg(options::OPT_fintelfpga)) {
DAL->AddFlagArg(0, Opts.getOption(options::OPT_MMD));
// if any -gN option is provided, use that.
if (Arg *A = Args.getLastArg(options::OPT_gN_Group))
DAL->append(A);
Expand Down
37 changes: 28 additions & 9 deletions clang/lib/Driver/ToolChains/Clang.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1138,6 +1138,16 @@ void Clang::AddPreprocessingOptions(Compilation &C, const JobAction &JA,
else
ArgM = ArgMD;

auto createFPGATempDepFile = [&](const char *&DepFile) {
// Generate dependency files as temporary. These will be used for the
// aoc call/bundled during fat object creation
std::string BaseName(Clang::getBaseInputName(Args, Inputs[0]));
std::string DepTmpName =
C.getDriver().GetTemporaryPath(llvm::sys::path::stem(BaseName), "d");
DepFile = C.addTempFile(C.getArgs().MakeArgString(DepTmpName));
C.getDriver().addFPGATempDepFile(DepFile, BaseName);
};

if (ArgM) {
// Determine the output location.
const char *DepFile;
Expand All @@ -1148,16 +1158,9 @@ void Clang::AddPreprocessingOptions(Compilation &C, const JobAction &JA,
DepFile = Output.getFilename();
} else if (!ArgMD) {
DepFile = "-";
} else if (ArgMD->getOption().matches(options::OPT_MMD) &&
Args.hasArg(options::OPT_fintelfpga) &&
} else if (Args.hasArg(options::OPT_fintelfpga) &&
JA.isDeviceOffloading(Action::OFK_SYCL)) {
// Generate dependency files as temporary. These will be used for the
// aoc call/bundled during fat object creation
std::string BaseName(Clang::getBaseInputName(Args, Inputs[0]));
std::string DepTmpName =
C.getDriver().GetTemporaryPath(llvm::sys::path::stem(BaseName), "d");
DepFile = C.addTempFile(C.getArgs().MakeArgString(DepTmpName));
C.getDriver().addFPGATempDepFile(DepFile, BaseName);
createFPGATempDepFile(DepFile);
} else {
DepFile = getDependencyFileName(Args, Inputs);
C.addFailureResultFile(DepFile, &JA);
Expand Down Expand Up @@ -1212,6 +1215,22 @@ void Clang::AddPreprocessingOptions(Compilation &C, const JobAction &JA,
CmdArgs.push_back("-module-file-deps");
}

if (!ArgM && Args.hasArg(options::OPT_fintelfpga) &&
JA.isDeviceOffloading(Action::OFK_SYCL)) {
// No dep generation option was provided, add all of the needed options
// to ensure a successful dep generation.
const char *DepFile;
createFPGATempDepFile(DepFile);
CmdArgs.push_back("-dependency-file");
CmdArgs.push_back(DepFile);
CmdArgs.push_back("-MT");
SmallString<128> P(Inputs[0].getBaseInput());
llvm::sys::path::replace_extension(P, "o");
SmallString<128> Quoted;
QuoteTarget(llvm::sys::path::filename(P), Quoted);
CmdArgs.push_back(Args.MakeArgString(Quoted));
Comment on lines +1227 to +1231
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Can we double-check these in the test?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I'll adjust the test accordingly. As for your -foffload-static-lib issue with .d question, this patch does not address that problem. For that problem, we need to extract the .d files from the archive and add them to the aoc call. Current device extraction only takes into account the device objects and passes them along to the partial link step. The .d files are left alone.

Copy link

@meiyacha meiyacha Jun 22, 2020 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I suppose this also affects offload static library that are passed without this flag?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@meiyacha, that is correct. Offload static lib w/ and w/out -foffload-static-lib behaves the same.

}

if (Args.hasArg(options::OPT_MG)) {
if (!ArgM || ArgM->getOption().matches(options::OPT_MD) ||
ArgM->getOption().matches(options::OPT_MMD))
Expand Down
14 changes: 12 additions & 2 deletions clang/test/Driver/sycl-offload-intelfpga.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -226,9 +226,19 @@
// RUN: | FileCheck -check-prefix=CHK-FPGA-DEP-FILES %s
// RUN: %clang_cl -### -fsycl -fintelfpga %t-1.cpp %t-2.cpp 2>&1 \
// RUN: | FileCheck -check-prefix=CHK-FPGA-DEP-FILES %s
// CHK-FPGA-DEP-FILES: clang{{.*}} "-dependency-file" "[[INPUT1:.+\.d]]"
// CHK-FPGA-DEP-FILES: clang{{.*}} "-dependency-file" "[[INPUT2:.+\.d]]"
// CHK-FPGA-DEP-FILES: clang{{.*}} "-dependency-file" "[[INPUT1:.+\.d]]" "-MT" "{{.*}}.o"
// CHK-FPGA-DEP-FILES: clang{{.*}} "-dependency-file" "[[INPUT2:.+\.d]]" "-MT" "{{.*}}.o"
// CHK-FPGA-DEP-FILES: aoc{{.*}} "-dep-files={{.*}}[[INPUT1]],{{.*}}[[INPUT2]]"
// CHK-FPGA-DEP-FILES-NOT: clang{{.*}} "-dependency-file" {{.*}} "-fsycl-is-host"

/// -fintelfpga dependency file check with host .d enabled
// RUN: %clangxx -### -MMD -fsycl -fintelfpga %t-1.cpp %t-2.cpp 2>&1 \
// RUN: | FileCheck -check-prefix=CHK-FPGA-DEP-FILES-HOST %s
// CHK-FPGA-DEP-FILES-HOST: clang{{.*}} "-dependency-file" "[[INPUT1:.+\.d]]" "-MT" "{{.*}}.o"
// CHK-FPGA-DEP-FILES-HOST: clang{{.*}} "-dependency-file" "[[INPUT2:.+\.d]]" "-MT" "{{.*}}.o"
// CHK-FPGA-DEP-FILES-HOST: aoc{{.*}} "-dep-files={{.*}}[[INPUT1]],{{.*}}[[INPUT2]]"
// CHK-FPGA-DEP-FILES-HOST: clang{{.*}} "-dependency-file" {{.*}} "-fsycl-is-host"
// CHK-FPGA-DEP-FILES-HOST: clang{{.*}} "-dependency-file" {{.*}} "-fsycl-is-host"

/// -fintelfpga dependency file generation test to object
// RUN: %clangxx -### -fsycl -fintelfpga %t-1.cpp %t-2.cpp -c 2>&1 \
Expand Down