[SYCL] Disable vectorizers in early optimizations

[AlexeySachkov]

No description provided.

[AlexeySachkov]

/summary:run

[bader]

Please, change the default value of SLPVectorize in SYCL mode to off, so we can still control SLP vectorizer using compiler options.
Basically, move the change to the driver/FE and add a regression test.

[bader]

BTW, it make sense to disable loop vectorizer by default as well.

[AlexeySachkov]

/summary:run

[bader]

LGTM, although I think the criteria for turning on/off optimizations should be target triple, rather than language mode.
I expect similar issues for SPIR target in OpenCL mode.

[bader]

@mdtoguchi, @AGindinson, could you take a look, please?

[keryell]

@aisoard @Ralender I am wondering whether this is good or bad for performance on Xilinx FPGA...

[AGindinson]

LGTM, thanks!

[bader]

@aisoard @Ralender I am wondering whether this is good or bad for performance on Xilinx FPGA...

@AlexeySachkov, I would prefer if we disable vectorizers only for SPIR target as I noted here. So if Xilinx FPGA uses different triple, it can still control the default behavior. NOTE: NVPTX, doesn't completely disables the vectorizer - https://github.com/intel/llvm/blob/sycl/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h#L65. It's not clear what is the impact on performance for NVPTX.

@keryell, note, this patch changes the default value, but vectorizers still can be enabled via command line options.

[AlexeySachkov]

@AlexeySachkov, I would prefer if we disable vectorizers only for SPIR target as I noted here. So if Xilinx FPGA uses different triple, it can still control the default behavior. NOTE: NVPTX, doesn't completely disables the vectorizer - https://github.com/intel/llvm/blob/sycl/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h#L65. It's not clear what is the impact on performance for NVPTX.

Ok, let's submit this patch as-is for now and I will prepare a follow-up PR to address your comment (submitted #2421 to track that and discuss)

[bader]

Thanks!