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[SYCL] Add new spellings for SYCL FPGA attributes #2568

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Merged
merged 16 commits into from
Oct 8, 2020
Merged

[SYCL] Add new spellings for SYCL FPGA attributes #2568

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0a6cfcf
[SYCL] Add new spellings for SYCL attributes
smanna12 Sep 29, 2020
e00629d
Fix clang-format issues
smanna12 Sep 30, 2020
2f63a30
Fix Clang-format issues
smanna12 Sep 30, 2020
5432ff3
Fix Clang-format issues
smanna12 Sep 30, 2020
c0cb1fe
Fix Clang-format issues
smanna12 Sep 30, 2020
7000c8e
update new patch to align with spec
smanna12 Oct 2, 2020
6f83e0f
Update some space issues
smanna12 Oct 2, 2020
6d6273f
Address review comments
smanna12 Oct 6, 2020
011037a
Fix clang formar issues
smanna12 Oct 6, 2020
3504536
Fix clang format issues and update unrelated test change
smanna12 Oct 6, 2020
f95d1b0
Address review comments
smanna12 Oct 7, 2020
99ea091
Fix clang-format issues
smanna12 Oct 7, 2020
5b99da8
Fix clang-format issues
smanna12 Oct 7, 2020
3e53d8d
Remove curly brances from one statement if condions
smanna12 Oct 7, 2020
3f58076
address review comments
smanna12 Oct 7, 2020
a922ebb
Fix clang-format issues
smanna12 Oct 7, 2020
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69 changes: 46 additions & 23 deletions clang/include/clang/Basic/Attr.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1216,7 +1216,8 @@ def SYCLIntelKernelArgsRestrict : InheritableAttr {
}

def SYCLIntelNumSimdWorkItems : InheritableAttr {
let Spellings = [CXX11<"intelfpga","num_simd_work_items">];
let Spellings = [CXX11<"intelfpga","num_simd_work_items">,
CXX11<"intel","num_simd_work_items">];
let Args = [ExprArgument<"Value">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let Subjects = SubjectList<[Function], ErrorDiag>;
Expand All @@ -1225,7 +1226,8 @@ def SYCLIntelNumSimdWorkItems : InheritableAttr {
}

def SYCLIntelMaxWorkGroupSize : InheritableAttr {
let Spellings = [CXX11<"intelfpga","max_work_group_size">];
let Spellings = [CXX11<"intelfpga","max_work_group_size">,
CXX11<"intel","max_work_group_size">];
let Args = [UnsignedArgument<"XDim">,
UnsignedArgument<"YDim">,
UnsignedArgument<"ZDim">];
Expand All @@ -1236,7 +1238,8 @@ def SYCLIntelMaxWorkGroupSize : InheritableAttr {
}

def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
let Spellings = [CXX11<"intelfpga","max_global_work_dim">];
let Spellings = [CXX11<"intelfpga","max_global_work_dim">,
CXX11<"intel","max_global_work_dim">];
let Args = [UnsignedArgument<"Number">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let Subjects = SubjectList<[Function], ErrorDiag>;
Expand All @@ -1245,7 +1248,8 @@ def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
}

def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
let Spellings = [CXX11<"intelfpga","no_global_work_offset">];
let Spellings = [CXX11<"intelfpga","no_global_work_offset">,
CXX11<"intel","no_global_work_offset">];
let Args = [BoolArgument<"Enabled", 1>];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let Subjects = SubjectList<[Function], ErrorDiag>;
Expand Down Expand Up @@ -1686,7 +1690,8 @@ def Mode : Attr {
}

def SYCLIntelFPGAIVDep : Attr {
let Spellings = [CXX11<"intelfpga","ivdep">];
let Spellings = [CXX11<"intelfpga","ivdep">,
CXX11<"intel","ivdep">];
let Args = [
ExprArgument<"SafelenExpr">, ExprArgument<"ArrayExpr">,
UnsignedArgument<"SafelenValue">
Expand Down Expand Up @@ -1732,7 +1737,8 @@ def SYCLIntelFPGAIVDep : Attr {
}

def SYCLIntelFPGAII : Attr {
let Spellings = [CXX11<"intelfpga","ii">];
let Spellings = [CXX11<"intelfpga","ii">,
CXX11<"intel","ii">];
let Args = [ExprArgument<"IntervalExpr">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let HasCustomTypeTransform = 1;
Expand All @@ -1745,7 +1751,8 @@ def SYCLIntelFPGAII : Attr {
}

def SYCLIntelFPGAMaxConcurrency : Attr {
let Spellings = [CXX11<"intelfpga","max_concurrency">];
let Spellings = [CXX11<"intelfpga","max_concurrency">,
CXX11<"intel","max_concurrency">];
let Args = [ExprArgument<"NThreadsExpr">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let HasCustomTypeTransform = 1;
Expand All @@ -1758,7 +1765,8 @@ def SYCLIntelFPGAMaxConcurrency : Attr {
}

def SYCLIntelFPGALoopCoalesce : Attr {
let Spellings = [CXX11<"intelfpga","loop_coalesce">];
let Spellings = [CXX11<"intelfpga","loop_coalesce">,
CXX11<"intel","loop_coalesce">];
let Args = [ExprArgument<"NExpr">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let HasCustomTypeTransform = 1;
Expand All @@ -1771,7 +1779,8 @@ def SYCLIntelFPGALoopCoalesce : Attr {
}

def SYCLIntelFPGADisableLoopPipelining : Attr {
let Spellings = [CXX11<"intelfpga","disable_loop_pipelining">];
let Spellings = [CXX11<"intelfpga","disable_loop_pipelining">,
CXX11<"intel","disable_loop_pipelining">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let HasCustomTypeTransform = 1;
let AdditionalMembers = [{
Expand All @@ -1783,7 +1792,8 @@ def SYCLIntelFPGADisableLoopPipelining : Attr {
}

def SYCLIntelFPGAMaxInterleaving : Attr {
let Spellings = [CXX11<"intelfpga","max_interleaving">];
let Spellings = [CXX11<"intelfpga","max_interleaving">,
CXX11<"intel","max_interleaving">];
let Args = [ExprArgument<"NExpr">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let HasCustomTypeTransform = 1;
Expand All @@ -1796,7 +1806,8 @@ def SYCLIntelFPGAMaxInterleaving : Attr {
}

def SYCLIntelFPGASpeculatedIterations : Attr {
let Spellings = [CXX11<"intelfpga","speculated_iterations">];
let Spellings = [CXX11<"intelfpga","speculated_iterations">,
CXX11<"intel","speculated_iterations">];
let Args = [ExprArgument<"NExpr">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let HasCustomTypeTransform = 1;
Expand Down Expand Up @@ -1841,23 +1852,26 @@ def IntelFPGALocalOrStaticVar : SubsetSubject<Var,
"local variables, static variables">;

def IntelFPGADoublePump : Attr {
let Spellings = [CXX11<"intelfpga", "doublepump">];
let Spellings = [CXX11<"intelfpga", "doublepump">,
CXX11<"intel", "doublepump">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let Documentation = [IntelFPGADoublePumpAttrDocs];
}

def IntelFPGASinglePump : Attr {
let Spellings = [CXX11<"intelfpga", "singlepump">];
let Spellings = [CXX11<"intelfpga", "singlepump">,
CXX11<"intel", "singlepump">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let Documentation = [IntelFPGASinglePumpAttrDocs];
}

def IntelFPGAMemory : Attr {
let Spellings = [CXX11<"intelfpga", "memory">];
let Spellings = [CXX11<"intelfpga", "memory">,
CXX11<"intel", "fpga_memory">];
let Args = [EnumArgument<"Kind", "MemoryKind",
["MLAB", "BLOCK_RAM", ""],
["MLAB", "BlockRAM", "Default"], 1>];
Expand All @@ -1877,7 +1891,8 @@ def IntelFPGAMemory : Attr {
}

def IntelFPGARegister : Attr {
let Spellings = [CXX11<"intelfpga", "register">];
let Spellings = [CXX11<"intelfpga", "register">,
CXX11<"intel", "fpga_register">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
Expand All @@ -1886,7 +1901,8 @@ def IntelFPGARegister : Attr {

// One integral argument.
def IntelFPGABankWidth : Attr {
let Spellings = [CXX11<"intelfpga","bankwidth">];
let Spellings = [CXX11<"intelfpga","bankwidth">,
CXX11<"intel","bankwidth">];
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
Field], ErrorDiag>;
Expand All @@ -1903,7 +1919,8 @@ def IntelFPGABankWidth : Attr {
}

def IntelFPGANumBanks : Attr {
let Spellings = [CXX11<"intelfpga","numbanks">];
let Spellings = [CXX11<"intelfpga","numbanks">,
CXX11<"intel","numbanks">];
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
Field], ErrorDiag>;
Expand All @@ -1920,7 +1937,8 @@ def IntelFPGANumBanks : Attr {
}

def IntelFPGAPrivateCopies : InheritableAttr {
let Spellings = [CXX11<"intelfpga","private_copies">];
let Spellings = [CXX11<"intelfpga","private_copies">,
CXX11<"intel","private_copies">];
let Args = [ExprArgument<"Value">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
Expand All @@ -1937,7 +1955,8 @@ def IntelFPGAPrivateCopies : InheritableAttr {

// Two string arguments.
def IntelFPGAMerge : Attr {
let Spellings = [CXX11<"intelfpga","merge">];
let Spellings = [CXX11<"intelfpga","merge">,
CXX11<"intel","merge">];
let Args = [StringArgument<"Name">, StringArgument<"Direction">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
Field], ErrorDiag>;
Expand All @@ -1946,7 +1965,8 @@ def IntelFPGAMerge : Attr {
}

def IntelFPGAMaxReplicates : Attr {
let Spellings = [CXX11<"intelfpga","max_replicates">];
let Spellings = [CXX11<"intelfpga","max_replicates">,
CXX11<"intel","max_replicates">];
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
Field], ErrorDiag>;
Expand All @@ -1963,7 +1983,8 @@ def IntelFPGAMaxReplicates : Attr {
}

def IntelFPGASimpleDualPort : Attr {
let Spellings = [CXX11<"intelfpga","simple_dual_port">];
let Spellings = [CXX11<"intelfpga","simple_dual_port">,
CXX11<"intel","simple_dual_port">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SYCLIsHost];
Expand All @@ -1988,7 +2009,8 @@ def SYCLIntelPipeIO : Attr {

// Variadic integral arguments.
def IntelFPGABankBits : Attr {
let Spellings = [CXX11<"intelfpga", "bank_bits">];
let Spellings = [CXX11<"intelfpga", "bank_bits">,
CXX11<"intel", "bank_bits">];
let Args = [VariadicExprArgument<"Args">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
Field], ErrorDiag>;
Expand All @@ -2005,7 +2027,8 @@ def IntelFPGABankBits : Attr {
}

def IntelFPGAForcePow2Depth : Attr {
let Spellings = [CXX11<"intelfpga","force_pow2_depth">];
let Spellings = [CXX11<"intelfpga","force_pow2_depth">,
CXX11<"intel","force_pow2_depth">];
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
Field], ErrorDiag>;
Expand Down
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