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[SYCL][CUDA][libclc] Add software atomics implementations for lower sm versions #5998

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Merged
merged 5 commits into from
Apr 25, 2022
Merged

[SYCL][CUDA][libclc] Add software atomics implementations for lower sm versions #5998

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8dc2efc
added software implementations for lower sm versions
t4c1 Apr 11, 2022
6722747
format
t4c1 Apr 11, 2022
b71f663
define SYCL_USE_NATIVE_FP_ATOMICSby default for cuda
t4c1 Apr 11, 2022
e6d997f
format
t4c1 Apr 11, 2022
ab49f16
fixed clanf macro test
t4c1 Apr 11, 2022
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5 changes: 3 additions & 2 deletions clang/lib/Frontend/InitPreprocessor.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1249,8 +1249,9 @@ static void InitializePredefinedMacros(const TargetInfo &TI,

const llvm::Triple &DeviceTriple = TI.getTriple();
const llvm::Triple::SubArchType DeviceSubArch = DeviceTriple.getSubArch();
if (DeviceTriple.isSPIR() &&
DeviceSubArch != llvm::Triple::SPIRSubArch_fpga)
if (DeviceTriple.isNVPTX() ||
(DeviceTriple.isSPIR() &&
DeviceSubArch != llvm::Triple::SPIRSubArch_fpga))
Builder.defineMacro("SYCL_USE_NATIVE_FP_ATOMICS");
// Enable generation of USM address spaces for FPGA.
if (DeviceSubArch == llvm::Triple::SPIRSubArch_fpga) {
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2 changes: 1 addition & 1 deletion clang/test/Preprocessor/sycl-macro-target-specific.cpp
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Expand Up @@ -20,7 +20,7 @@
// RUN: %clang_cc1 %s -fsycl-is-device -triple spir64_fpga-unknown-unknown -E -dM \
// RUN: | FileCheck --check-prefix=CHECK-SYCL-FP-ATOMICS-NEG %s
// RUN: %clang_cc1 %s -fsycl-is-device -triple nvptx64-nvidia-nvcl -E -dM \
// RUN: | FileCheck --check-prefix=CHECK-SYCL-FP-ATOMICS-NEG %s
// RUN: | FileCheck --check-prefix=CHECK-SYCL-FP-ATOMICS %s
// CHECK-SYCL-FP-ATOMICS: #define SYCL_USE_NATIVE_FP_ATOMICS
// CHECK-SYCL-FP-ATOMICS-NEG-NOT: #define SYCL_USE_NATIVE_FP_ATOMICS

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93 changes: 92 additions & 1 deletion libclc/ptx-nvidiacl/libspirv/atomic/atomic_add.cl
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Expand Up @@ -17,7 +17,98 @@ __CLC_NVVM_ATOMIC(ulong, m, long, l, add, _Z18__spirv_AtomicIAdd)

__CLC_NVVM_ATOMIC(float, f, float, f, add, _Z21__spirv_AtomicFAddEXT)
#ifdef cl_khr_int64_base_atomics
__CLC_NVVM_ATOMIC(double, d, double, d, add, _Z21__spirv_AtomicFAddEXT)

#define __CLC_NVVM_ATOMIC_ADD_DOUBLE_IMPL(ADDR_SPACE, ADDR_SPACE_MANGLED, \
ADDR_SPACE_NV, SUBSTITUTION1, \
SUBSTITUTION2) \
long \
_Z18__spirv_AtomicLoadP##ADDR_SPACE_MANGLED##KlN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE( \
volatile ADDR_SPACE const long *, enum Scope, \
enum MemorySemanticsMask); \
long \
_Z29__spirv_AtomicCompareExchange##P##ADDR_SPACE_MANGLED##lN5__spv5Scope4FlagENS##SUBSTITUTION1##_19MemorySemanticsMask4FlagES##SUBSTITUTION2##_ll( \
volatile ADDR_SPACE long *, enum Scope, enum MemorySemanticsMask, \
enum MemorySemanticsMask, long, long); \
__attribute__((always_inline)) _CLC_DECL double \
_Z21__spirv_AtomicFAddEXT##P##ADDR_SPACE_MANGLED##d##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##d( \
volatile ADDR_SPACE double *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics, double value) { \
/* Semantics mask may include memory order, storage class and other info \
Memory order is stored in the lowest 5 bits */ \
unsigned int order = semantics & 0x1F; \
if (__clc_nvvm_reflect_arch() >= 600) { \
switch (order) { \
case None: \
__CLC_NVVM_ATOMIC_IMPL_ORDER(double, double, d, add, ADDR_SPACE, \
ADDR_SPACE_NV, ) \
break; \
case Acquire: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(double, double, d, add, ADDR_SPACE, \
ADDR_SPACE_NV, _acquire) \
} else { \
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(double, double, d, add, \
ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
case Release: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(double, double, d, add, ADDR_SPACE, \
ADDR_SPACE_NV, _release) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_IMPL_ORDER(double, double, d, add, ADDR_SPACE, \
ADDR_SPACE_NV, ) \
} \
break; \
case AcquireRelease: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_IMPL_ORDER(double, double, d, add, ADDR_SPACE, \
ADDR_SPACE_NV, _acq_rel) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(double, double, d, add, \
ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
} \
__builtin_trap(); \
__builtin_unreachable(); \
} else { \
enum MemorySemanticsMask load_order; \
switch (semantics) { \
case SequentiallyConsistent: \
load_order = SequentiallyConsistent; \
break; \
case Acquire: \
case AcquireRelease: \
load_order = Acquire; \
break; \
default: \
load_order = None; \
} \
volatile ADDR_SPACE long *pointer_int = \
(volatile ADDR_SPACE long *)pointer; \
long old_int; \
long new_val_int; \
do { \
old_int = \
_Z18__spirv_AtomicLoadP##ADDR_SPACE_MANGLED##KlN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE( \
pointer_int, scope, load_order); \
double new_val = *(double *)&old_int + *(double *)&value; \
new_val_int = *(long *)&new_val; \
} while ( \
_Z29__spirv_AtomicCompareExchange##P##ADDR_SPACE_MANGLED##lN5__spv5Scope4FlagENS##SUBSTITUTION1##_19MemorySemanticsMask4FlagES##SUBSTITUTION2##_ll( \
pointer_int, scope, semantics, semantics, new_val_int, \
old_int) != old_int); \
return *(double *)&old_int; \
} \
}

__CLC_NVVM_ATOMIC_ADD_DOUBLE_IMPL(, , _gen_, 0, 4)
__CLC_NVVM_ATOMIC_ADD_DOUBLE_IMPL(__global, U3AS1, _global_, 1, 5)
__CLC_NVVM_ATOMIC_ADD_DOUBLE_IMPL(__local, U3AS3, _shared_, 1, 5)

#endif

#undef __CLC_NVVM_ATOMIC_TYPES
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