[SYCL][Matrix] Fix __spirv_JointMatrixINTEL signature

[MrSidims]

Default SYCL_EXT_ONEAPI_MATRIX to 1

Added SYCL_EXT_ONEAPI_MATRIX_VERSION to differentiate API versions.

Only add 'Use' parameter if testing macro SYCL_EXT_ONEAPI_MATRIX_VERSION = 2
is defined.

Signed-off-by: Sidorov, Dmitry [email protected]

[romanovvlad]

Could you please clarify where this macro is defined? I've got an impression that the macro should be defined to some specific value in our headers.

[dkhaldi]

The macro is defined here: https://github.com/intel/llvm/blob/sycl/sycl/include/sycl/feature_test.hpp.in

[MrSidims]

@JackAKirk it doesn't look like a correct usage of SYCL_EXT_ONEAPI_MATRIX (users shouldn't pass such macro during compilation, see #6662 (comment) ). What would be an appropriate replacement for it?

[JackAKirk]

There isn't an intention of using any macro in the future in order to decide the APIs to use. Initially for the initial Tensor Cores experimental implementation we followed the existing pattern used by the AOT and JIT intel implementations by setting a new value to the feature test macro. The SYCL spec itself doesn't appear to forbid this, although it sounds like the extension document itself contradicts the implementation in this regard!

We plan to add a separate macro analogous to SYCL_EXT_ONEAPI_MATRIX_LEGACY_API. We could name it SYCL_EXT_ONEAPI_MATRIX_LEGACY_CUDA_API for example.
Since the interfaces for the combined Intel/CUDA implementation has been decided I could also open a PR that supports both Intel and CUDA backends within the same implementation. #5920 is blocked on a spirv builtin atm, so it sounds like we shouldn't wait on this PR before starting the combined implementation. We could add the macro for the legacy version at the same time.

[gmlueck]

I just talked with @dkhaldi, and it sounds like she prefers to have a different name for the macro that chooses the API.

[MrSidims]

/verify

[MrSidims]

/verify with intel/llvm-test-suite#1311

[dkhaldi]

LGTM

[MrSidims]

/verify with intel/llvm-test-suite#1311

[MrSidims]

It does look like verify with doesn't attach tests from llvm-test-suite, so will try to do testing from an opposite direction.

[MrSidims]

@romanovvlad could you please take one more look? I can't tell for sure, why 'verify with' is failing for CUDA in this PR. At the same time in intel/llvm-test-suite#1311 CUDA tests are passing with this PR attached.

[MrSidims]

@intel/llvm-gatekeepers could you please take a look and merge?
(should be merged together with intel/llvm-test-suite#1311 )

[pvchupin]

@romanovvlad could you please take one more look? I can't tell for sure, why 'verify with' is failing for CUDA in this PR. At the same time in intel/llvm-test-suite#1311 CUDA tests are passing with this PR attached.

CUDA doesn't run in "verify with" mode. Have you checked tests modifications locally on CUDA?

[MrSidims]

@romanovvlad could you please take one more look? I can't tell for sure, why 'verify with' is failing for CUDA in this PR. At the same time in intel/llvm-test-suite#1311 CUDA tests are passing with this PR attached.

CUDA doesn't run in "verify with" mode. Have you checked tests modifications locally on CUDA?

No, I didn't . I've just tried and in both cases with and without the patch the tests are failing to compile. Trying to figure out, what else is missing.

I would assume that the fact of successful compilation of the tests is good enough since CUDA is only affected by modification of a macro.

[MrSidims]

Made an NFC update for exceptions' messages.
@pvchupin on the machine with CUDA I was able to compile device-code of the tests successfully (and only device code is affected by the changes and there is no difference in IR before and after the patch but clang version metadata, so it's good enough).
Though wasn't able to execute the binaries yet. I would still need to learn, how to work with CUDA properly, but meanwhile, can we merged these 2 PRs?

[MrSidims]

Made an NFC update for exceptions' messages. @pvchupin on the machine with CUDA I was able to compile device-code of the tests successfully (and only device code is affected by the changes and there is no difference in IR before and after the patch but clang version metadata, so it's good enough). Though wasn't able to execute the binaries yet. I would still need to learn, how to work with CUDA properly, but meanwhile, can we merged these 2 PRs?

With a help from Steffen was able to compile not only the device code, but all the test. All went fine. Execution though actually requires something like A1000 to run AMX code.