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[SYCL][ESIMD] Fix an issue with intrinsic generation #7026

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merged 2 commits into from
Oct 17, 2022
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[SYCL][ESIMD] Fix an issue with intrinsic generation #7026

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9de62b8
Fix an issue with intrinsic generation
fineg74 Oct 11, 2022
07b9fb0
Fix a test failure
fineg74 Oct 12, 2022
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4 changes: 2 additions & 2 deletions llvm/lib/SYCLLowerIR/ESIMD/LowerESIMD.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -328,14 +328,14 @@ class ESIMDIntrinDescTable {
{"rdregion",
{"rdregion", {a(0), t(3), t(4), t(5), a(1), t(6)}, nk(-1)}},
{"rdindirect",
{"rdregion", {a(0), c32(0), t(2), c32(0), a(1), t(3)}, nk(-1)}},
{"rdregion", {a(0), c32(0), c32(1), c32(0), a(1), t(3)}, nk(-1)}},
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what this argument means
### * arg3: i32 stride in elements, constant
? It is strange it is forced to constant 1

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oh, it is
### * arg2: i32 width in elements, constant
why it is forced to 1?

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I talked to @vmustya, 1 for indirect version means "number of elements per offset", so it seems correct.

{{"wrregion"},
{{"wrregion"},
{a(0), a(1), t(3), t(4), t(5), a(2), t(6), ai1(3)},
nk(-1)}},
{{"wrindirect"},
{{"wrregion"},
{a(0), a(1), c32(0), t(2), c32(0), a(2), t(3), ai1(3)},
{a(0), a(1), c32(0), c32(1), c32(0), a(2), t(3), ai1(3)},
nk(-1)}},
{"vload", {"vload", {l(0)}}},
{"vstore", {"vstore", {a(1), a(0)}}},
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6 changes: 3 additions & 3 deletions llvm/test/SYCLLowerIR/ESIMD/lower_intrins.ll
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Expand Up @@ -21,7 +21,7 @@ target triple = "spir64-unknown-unknown"
@vg = dso_local global %"cm::gen::simd<int, 16>" zeroinitializer, align 64 #0
@vc = dso_local addrspace(1) global <32 x i32> zeroinitializer

; LowerESIMD pass should process every function,
; LowerESIMD pass should process every function,
; !sycl_explicit_simd metadata is not necessary.

define dso_local spir_func <16 x i16> @FUNC_8() {
Expand Down Expand Up @@ -197,7 +197,7 @@ define dso_local spir_func <8 x i32> @FUNC_43() {
%a_2 = alloca <8 x i16>
%2 = load <8 x i16>, <8 x i16>* %a_2
%ret_val = call spir_func <8 x i32> @_Z18__esimd_rdindirectIiLi16ELi8ELi0EEN2cl4sycl3ext5intel3gpu11vector_typeIT_XT1_EE4typeENS4_IS5_XT0_EE4typeENS4_ItXT1_EE4typeE(<16 x i32> %1, <8 x i16> %2)
; CHECK: %{{[0-9a-zA-Z_.]+}} = call <8 x i32> @llvm.genx.rdregioni.v8i32.v16i32.v8i16(<16 x i32> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 8, i32 0, <8 x i16> %{{[0-9a-zA-Z_.]+}}, i32 0)
; CHECK: %{{[0-9a-zA-Z_.]+}} = call <8 x i32> @llvm.genx.rdregioni.v8i32.v16i32.v8i16(<16 x i32> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 1, i32 0, <8 x i16> %{{[0-9a-zA-Z_.]+}}, i32 0)
ret <8 x i32> %ret_val
}

Expand All @@ -209,7 +209,7 @@ define dso_local spir_func <16 x i32> @FUNC_44() {
%a_3 = alloca <8 x i16>
%3 = load <8 x i16>, <8 x i16>* %a_3
%ret_val = call spir_func <16 x i32> @_Z18__esimd_wrindirectIiLi16ELi8ELi0EEN2cl4sycl3ext5intel3gpu11vector_typeIT_XT0_EE4typeES7_NS4_IS5_XT1_EE4typeENS4_ItXT1_EE4typeESB_(<16 x i32> %1, <8 x i32> %2, <8 x i16> %3, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
; CHECK: %{{[0-9a-zA-Z_.]+}} = call <16 x i32> @llvm.genx.wrregioni.v16i32.v8i32.v8i16.v8i1(<16 x i32> %{{[0-9a-zA-Z_.]+}}, <8 x i32> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 8, i32 0, <8 x i16> %{{[0-9a-zA-Z_.]+}}, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
; CHECK: %{{[0-9a-zA-Z_.]+}} = call <16 x i32> @llvm.genx.wrregioni.v16i32.v8i32.v8i16.v8i1(<16 x i32> %{{[0-9a-zA-Z_.]+}}, <8 x i32> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 1, i32 0, <8 x i16> %{{[0-9a-zA-Z_.]+}}, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
ret <16 x i32> %ret_val
}

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