LLVM and SPIRV-LLVM-Translator pulldown (WW46) #7317
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…address space The 32-bit floating-point atomic add instructions on AMDGPUs does not support a "flat" or "generic" address space. So, if the address space cannot be determined statically, the AMDGPU backend will fall back to a CAS loop (which does support "flat" addressing). Instead, this patch emits runtime address-space checks to allow native FP atomic add instructions for global and LDS memory (and non-atomic FP add instructions for private/scratch memory). In order to do that, this patch introduces a new interface function `emitExpandAtomicRMW`. It is expected to be called when a common atomic expand doesn't work for a specific target, such as the case we discussed here. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D129690
Additional SCEV verification highlighted a case where the cached loop dispositions where incorrect after simplifying a phi node in IndVars. Fix it by invalidating the phi before replacing it. Fixes #58750
This truncation can be unexpected and break program behavior. Dedicated emulation passes should be used instead. Also rename pass options to "emulate-lt-32-bit-scalar-types". Fixes: llvm/llvm-project#57917 Reviewed By: antiagainst Differential Revision: https://reviews.llvm.org/D137115
Reviewed By: antiagainst Differential Revision: https://reviews.llvm.org/D137166
The defining Op may live in an unlinked block so its parent Op may be null. Only assert it when the parent Op is not null. Reviewed By: mravishankar Differential Revision: https://reviews.llvm.org/D137306
…n the same line. Cases such as those in the associated lit tests, can now be supported. This adds a 'Count' field to TargetRegionEntryInfo to differentiate regions with the same source position. The OffloadEntriesInfoManager routines are updated to maintain a count of regions seen at a location. The registration of regions proceeds that same as before, but now the next available count is always determined and used in the offload entry. Fixes: llvm/llvm-project#52707 Differential Revision: https://reviews.llvm.org/D134816
Fix placement of ifdefs in hugify.cpp after D129107 landed.
We should always move jump tables when requested. Previously, we were not moving jump tables of non-simple functions in relocation mode. That caused a bug detailed in the attached test case: in PIC jump tables, we force jump tables to be moved, but if they are not moved because the function is not simple, we could incorrectly update original entries in .rodata, corrupting it under special circumstances (see testcase). Reviewed By: #bolt, maksfb Differential Revision: https://reviews.llvm.org/D137357
Differential revision: https://reviews.llvm.org/D136889
Some operations need to generate multiple operations when implementing the tiling interface. Here is a sound example in IREE, see iree-org/iree#10905 for more details. Reviewed By: mravishankar Differential Revision: https://reviews.llvm.org/D137300
…native target is enabled This is for case when native target like X86 is not in LLVM_TARGETS_TO_BUILD. Right now LLVM_DEFAULT_TARGET_TRIPLE is set to LLVM_HOST_TRIPLE even when native target is not enabled, As a result, many lit tests will fail because default_triple is set for lit test but not enabled when build LLVM. Reviewed By: smeenai Differential Revision: https://reviews.llvm.org/D134972
This allows for bitcast conversion to roundtrip. Fixes: llvm/llvm-project#58801 Reviewed By: antiagainst, Hardcode84, mravishankar Differential Revision: https://reviews.llvm.org/D137459
This test is broken due to the flaky encoding of top-level JSON key 'memory' When I run locally (linux) the test passed. However, it failed the build bot: https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/48111/ I will find a way to repro before I can actually fix this issue correctly. https://reviews.llvm.org/D137455
This was trying to add segments beyond the new and use, so skip additional segments. This would hit (S < E && "Cannot create empty or backwards segment").
It is caused by regenerate captured var value when processing the has_device_addr, the captured var value has been generated in GenerateOpenMPCapturedVars and passed as Arg in generateInfoForCapture. The fix just use Arg instead regenerated just same as is_device_ptr
This reverts commit e3ccbae. There is a bug which is failing the test running on mac.
Reviewed By: aartbik Differential Revision: https://reviews.llvm.org/D135927
This matches the behavior in instcombine, and for fdiv.
Sometimes libc++'s stddef.h wrapper gets included, which defines ::nullptr_t. This test is compiled with -Wshadow -Werror, so shadowing ::nullptr_t with a nullptr_t in main is an error. Include cstddef, which is guaranteed to define std::nullptr_t in C++11 and forward. Reviewed By: ldionne, #libc_abi Differential Revision: https://reviews.llvm.org/D137127
In `MLInlineAdvisor::getAdviceImpl`, we call `getCachedFPI` twice, once for the caller, once for the callee, so the second may invalidate the reference obtained by the first because the underlying implementation of the cache is a `DenseMap`. `std::map` doesn't have that problem.
inc/dec are not add/sub of 1.
Reviewed By: aartbik Differential Revision: https://reviews.llvm.org/D137463
…gate sparse tensor SSA properly. Reviewed By: aartbik Differential Revision: https://reviews.llvm.org/D137468
Previously, we only checked for duplicate zero entries when merging a MemOPSize table (see D92074), but a user recently provided a reproducer demonstrating that other entries can also be duplicated. As demonstrated by the test in this patch, PGOMemOPSizeOpt can potentially generate invalid IR for non-zero, non-consecutive duplicate entries. This seems to be a rare case, since the duplicate entry is often below the threshold, but possible. This patch extends the existing warning to check for any duplicate values in the table, both in the optimization and in llvm-profdata. Differential Revision: https://reviews.llvm.org/D136211
But I can not reproduce the problem on my local machine. My local machine run: 222 0x5a6780 222 0x7fffbef9400e 222 0x5a677e 0x5a6780 0x7fffbef936c8 222 0x376f8e 0x376f90 0x7fffbef94008 222 0x281f20 222 0x7fffbef9400e PASSED
Adds support for selecting the following instructions using GlobalISel: - v_mad_mix/v_fma_mix - v_mad_mixhi/v_fma_mixhi - v_mad_mixlo/v_fma_mixlo To select those instructions properly, some additional changes were needed which impacted other tests as well. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D134354
Insert constants and globals in order by maintaining the position of the constant and global inserted last. Update the tests to reflect the updated insertion order. Also make sure functions are always inserted at the end of the module instead of at the second last position and delete a spurious function in the intrinsic.ll that seems to exist to avoid the first function under test ends up at the end of the module. Reviewed By: ftynse Differential Revision: https://reviews.llvm.org/D136679
This extension adds conversion instruction from float to tensor float (TF32) data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead instruction below uses 32-bit float type to represent TF32 value. Spec: intel#6990 Signed-off-by: Sidorov, Dmitry <[email protected]> Original commit: KhronosGroup/SPIRV-LLVM-Translator@ea3ddc1
) Community restricted readnone, readonly and writeonly attributes to be only function parameter attributes. This patch aligns the translator with llvm.org. It also fixes a bug, when readnone attribute is being mapped to NoWrite SPIR-V function parameter attribute. Signed-off-by: Sidorov, Dmitry <[email protected]> Signed-off-by: Sidorov, Dmitry <[email protected]> Original commit: KhronosGroup/SPIRV-LLVM-Translator@c1fe5fe
One of the reasons behind this change is to make code more easily deal with the
future prospect of opaque types, so that helper methods (like adjusting image
types) can handle both pointer type and opaque type representations simply by
querying if the input type is a TypedPointerType or an OpaqueType [name for the
latter still pending].
The set of changes are:
* OCLTypeToSPIRV now uses TypedPointerType internally
* adaptSPIRVImageType and getSPIRVStructTypeByChangeBaseTypeName are collapsed
into one method (adjustImageType) that works with TypedPointerTypes.
* A few is*StructType methods have been reverted back to is*Type methods, taking
a TypedPointerType parameter instead.
* BuiltinCallHelper::addSPIRVCall{Pair} allows for the creation of SPIR-V calls
that can use TypedPointerType or actual type for parameters and return value.
* BuiltinCallHelper::getCallValue{Type} is a simple helper that hides many of
the uses of getParameterTypes.
* The Type* parameter of the callback in BuiltinCallMutator::mapArg now provides
a TypedPointerType or the actual type, instead of the pointer element type.
* BuiltinCallMutator::ValueTypePair similarly takes a TypedPointerType or the
actual type.
* getParameterTypes (when passed a SmallVector<Type *>) does a similar thing.
(The SmallVector<TypedPointerType *> variant has been removed in favor of only
using the other one.)
Note that the last few changes do change the semantics of function parameters
without changing the function name or signature.
Co-authored-by: Dmitry Sidorov <[email protected]>
Original commit:
KhronosGroup/SPIRV-LLVM-Translator@5ce6a99
Fznamznon
added
the
disable-lint
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Unrelated failure: SYCL :: Regression/device_num.cpp - Fix in #7336. |
Fznamznon
commented
Nov 10, 2022
This reverts commit d9d8669.
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Unrelated failure SYCL :: Basic/barrier_order.cpp - Reported in #7330. Temporarily disabled in intel/llvm-test-suite#1376. |
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Jenkins/Precommit seems to be failing for infrastructural reason. I reported it. |
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/merge |
bb-sycl
approved these changes
Nov 10, 2022
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Thu 10 Nov 2022 08:12:04 PM UTC --- Start to merge the commit into sycl branch. It will take several minutes. |
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Thu 10 Nov 2022 08:16:23 PM UTC --- Merge the branch in this PR to base automatically. Will close the PR later. |
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LLVM: llvm/llvm-project@9aae3dd
SPIRV-LLVM-Translator: KhronosGroup/SPIRV-LLVM-Translator@bdc5988