[SYCL][Level Zero] Implement sycl_ext_intel_cslice extension #7626
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With this change, on PVC sub-sub-devices now require info::partition_property::ext_intel_partition_by_cslice instead of info::partition_property::partition_by_affinity_domain that wasn't quite accurately describing the actual scheme. On other devices, CSlice-based partitioning is now disabled because that's not how the actual H/W works. If precise manual access to individual CCS is required than sycl_ext_intel_queue_index extension should be used instead. Extension specification is being added in intel#7513.
aelovikov-intel
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Implementation is being done in intel/llvm#7626
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There is more work to be done, but I think that could be handled in separate PRs. Possibly incomplete list:
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romanovvlad
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Dec 4, 2022
againull
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Dec 5, 2022
| @@ -4172,6 +4172,7 @@ _ZNK4sycl3_V16device14is_acceleratorEv | |||
| _ZNK4sycl3_V16device18create_sub_devicesILNS0_4info18partition_propertyE4230EEESt6vectorIS1_SaIS1_EEm | |||
| _ZNK4sycl3_V16device18create_sub_devicesILNS0_4info18partition_propertyE4231EEESt6vectorIS1_SaIS1_EERKS5_ImSaImEE | |||
| _ZNK4sycl3_V16device18create_sub_devicesILNS0_4info18partition_propertyE4232EEESt6vectorIS1_SaIS1_EENS3_25partition_affinity_domainE | |||
| _ZNK4sycl3_V16device18create_sub_devicesILNS0_4info18partition_propertyE4233EEESt6vectorIS1_SaIS1_EEv | |||
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Please update Windows symbols as well.
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Local windows build is broken for me. I'm working with @steffenlarsen on resolving this.
Version bump have to be major actually.
bader
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Dec 6, 2022
bader
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Dec 7, 2022
This was referenced Dec 8, 2022
…ARTITION_BY_CSLICE
…EXPOSE_CSLICE_IN_AFFINITY_PARTITIONING For backward compatibility and should really be addressed by customers ASAP because the behavior might be different from what they expect.
smaslov-intel
approved these changes
Dec 10, 2022
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@steffenlarsen would you please approve the docs change and merge? |
pvchupin
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Dec 13, 2022
) Implementation is being done in intel/llvm#7626
againull
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Recently, an extension was added here: #7513 This extension allows partitioning a device by "cslice" (aka CCS-es). With this change, on PVC sub-sub-devices now require info::partition_property::ext_intel_partition_by_cslice instead of info::partition_property::partition_by_affinity_domain that wasn't quite accurately describing the actual scheme. Level Zero backend support was added here: #7626 In this change, we are adding support in OpenCL plugin. This change makes use of the cl_intel_command_queue_families recently added. Signed-off-by: Arvind Sudarsanam <[email protected]>
aelovikov-intel
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…tel/llvm-test-suite#1434) Implementation is being done in intel#7626
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With this change, on PVC sub-sub-devices now require
info::partition_property::ext_intel_partition_by_csliceinstead ofinfo::partition_property::partition_by_affinity_domainthat wasn't quite accurately describing the actual scheme.The old behavior could be temporarily restored via
SYCL_PI_LEVEL_ZERO_EXPOSE_CSLICE_IN_AFFINITY_PARTITIONINGenvironment variable but it is immediately deprecated, and customers are encouraged to switch to the new partitioning scheme as soon as possible.However, even in this scenario,
sub_sub_device.get_info<info::device::partition_type_property>()would returninfo::partition_property::ext_intel_partition_by_cslice. That is due to the fact that the whole device hierarchy is pre-populated in the plugin, and we don't know in advance what partitioning would be used inget_sub_devicescall from SYCL RT.On other devices, CSlice-based partitioning is now disabled because that's not how the actual H/W works. If precise manual access to individual CCS is required than
sycl_ext_intel_queue_indexextension should be used instead.Extension specification is being added in #7513.