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[SYCL] Change lowering of 'cl::sycl::select' into SPIR-V #904

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Merged
merged 1 commit into from
Dec 6, 2019
Merged

[SYCL] Change lowering of 'cl::sycl::select' into SPIR-V #904

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16 changes: 8 additions & 8 deletions sycl/include/CL/sycl/builtins.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1303,7 +1303,7 @@ detail::enable_if_t<
detail::is_geninteger<T>::value && detail::is_igeninteger<T2>::value, T>
select(T a, T b, T2 c) __NOEXC {
detail::check_vector_size<T, T2>();
return __sycl_std::__invoke_Select<T>(detail::select_arg_c_t<T2>(c), b, a);
return __sycl_std::__invoke_select<T>(a, b, c);
}

// geninteger select (geninteger a, geninteger b, ugeninteger c)
Expand All @@ -1312,7 +1312,7 @@ detail::enable_if_t<
detail::is_geninteger<T>::value && detail::is_ugeninteger<T2>::value, T>
select(T a, T b, T2 c) __NOEXC {
detail::check_vector_size<T, T2>();
return __sycl_std::__invoke_Select<T>(detail::select_arg_c_t<T2>(c), b, a);
return __sycl_std::__invoke_select<T>(a, b, c);
}

// genfloatf select (genfloatf a, genfloatf b, genint c)
Expand All @@ -1321,7 +1321,7 @@ detail::enable_if_t<
detail::is_genfloatf<T>::value && detail::is_genint<T2>::value, T>
select(T a, T b, T2 c) __NOEXC {
detail::check_vector_size<T, T2>();
return __sycl_std::__invoke_Select<T>(detail::select_arg_c_t<T2>(c), b, a);
return __sycl_std::__invoke_select<T>(a, b, c);
}

// genfloatf select (genfloatf a, genfloatf b, ugenint c)
Expand All @@ -1330,7 +1330,7 @@ detail::enable_if_t<
detail::is_genfloatf<T>::value && detail::is_ugenint<T2>::value, T>
select(T a, T b, T2 c) __NOEXC {
detail::check_vector_size<T, T2>();
return __sycl_std::__invoke_Select<T>(detail::select_arg_c_t<T2>(c), b, a);
return __sycl_std::__invoke_select<T>(a, b, c);
}

// genfloatd select (genfloatd a, genfloatd b, igeninteger64 c)
Expand All @@ -1339,7 +1339,7 @@ detail::enable_if_t<
detail::is_genfloatd<T>::value && detail::is_igeninteger64bit<T2>::value, T>
select(T a, T b, T2 c) __NOEXC {
detail::check_vector_size<T, T2>();
return __sycl_std::__invoke_Select<T>(detail::select_arg_c_t<T2>(c), b, a);
return __sycl_std::__invoke_select<T>(a, b, c);
}

// genfloatd select (genfloatd a, genfloatd b, ugeninteger64 c)
Expand All @@ -1348,7 +1348,7 @@ detail::enable_if_t<
detail::is_genfloatd<T>::value && detail::is_ugeninteger64bit<T2>::value, T>
select(T a, T b, T2 c) __NOEXC {
detail::check_vector_size<T, T2>();
return __sycl_std::__invoke_Select<T>(detail::select_arg_c_t<T2>(c), b, a);
return __sycl_std::__invoke_select<T>(a, b, c);
}

// genfloath select (genfloath a, genfloath b, igeninteger16 c)
Expand All @@ -1357,7 +1357,7 @@ detail::enable_if_t<
detail::is_genfloath<T>::value && detail::is_igeninteger16bit<T2>::value, T>
select(T a, T b, T2 c) __NOEXC {
detail::check_vector_size<T, T2>();
return __sycl_std::__invoke_Select<T>(detail::select_arg_c_t<T2>(c), b, a);
return __sycl_std::__invoke_select<T>(a, b, c);
}

// genfloath select (genfloath a, genfloath b, ugeninteger16 c)
Expand All @@ -1366,7 +1366,7 @@ detail::enable_if_t<
detail::is_genfloath<T>::value && detail::is_ugeninteger16bit<T2>::value, T>
select(T a, T b, T2 c) __NOEXC {
detail::check_vector_size<T, T2>();
return __sycl_std::__invoke_Select<T>(detail::select_arg_c_t<T2>(c), b, a);
return __sycl_std::__invoke_select<T>(a, b, c);
}

namespace native {
Expand Down
2 changes: 1 addition & 1 deletion sycl/include/CL/sycl/detail/builtins.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -239,7 +239,7 @@ MAKE_CALL_ARG1(SignBitSet, __FUNC_PREFIX_CORE) // signbit
MAKE_CALL_ARG1(Any, __FUNC_PREFIX_CORE) // any
MAKE_CALL_ARG1(All, __FUNC_PREFIX_CORE) // all
MAKE_CALL_ARG3(bitselect, __FUNC_PREFIX_OCL)
MAKE_CALL_ARG3(Select, __FUNC_PREFIX_CORE) // select
MAKE_CALL_ARG3(select, __FUNC_PREFIX_OCL) // select
#ifndef __SYCL_DEVICE_ONLY__
} // namespace __host_std
} // namespace cl
Expand Down
12 changes: 0 additions & 12 deletions sycl/include/CL/sycl/detail/generic_type_traits.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -484,18 +484,6 @@ template <typename T> struct RelationalReturnType {
#endif
};

// Used for select built-in function
template <typename T> struct SelectWrapperTypeArgC {
#ifdef __SYCL_DEVICE_ONLY__
using type = Boolean<TryToGetNumElements<T>::value>;
#else
using type = T;
#endif
};

template <typename T>
using select_arg_c_t = typename SelectWrapperTypeArgC<T>::type;

template <typename T> using rel_ret_t = typename RelationalReturnType<T>::type;

// Used for any and all built-in functions
Expand Down
70 changes: 35 additions & 35 deletions sycl/source/detail/builtins_relational.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -121,11 +121,11 @@ typename std::enable_if<d::is_sgenfloat<T>::value, T>::type inline __bitselect(
return br.f;
}

template <typename T, typename T2> inline T2 __Select(T c, T2 b, T2 a) {
template <typename T, typename T2> inline T2 __select(T2 a, T2 b, T c) {
return (c ? b : a);
}

template <typename T, typename T2> inline T2 __vSelect(T c, T2 b, T2 a) {
template <typename T, typename T2> inline T2 __vselect(T2 a, T2 b, T c) {
return d::msbIsSet(c) ? b : a;
}
} // namespace
Expand Down Expand Up @@ -407,49 +407,49 @@ MAKE_SC_1V_2V_3V(bitselect, s::cl_half, s::cl_half, s::cl_half, s::cl_half)
// (Select) // select
// for scalar: result = c ? b : a.
// for vector: result[i] = (MSB of c[i] is set)? b[i] : a[i]
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_float, s::cl_int, s::cl_float,
s::cl_float)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_float, s::cl_uint, s::cl_float,
s::cl_float)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_double, s::cl_long,
s::cl_double, s::cl_double)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_double, s::cl_ulong,
s::cl_double, s::cl_double)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_char, s::cl_char, s::cl_char,
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_float, s::cl_float,
s::cl_float, s::cl_int)
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_float, s::cl_float,
s::cl_float, s::cl_uint)
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_double, s::cl_double,
s::cl_double, s::cl_long)
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_double, s::cl_double,
s::cl_double, s::cl_ulong)
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_char, s::cl_char, s::cl_char,
s::cl_char)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_char, s::cl_uchar, s::cl_char,
s::cl_char)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_uchar, s::cl_char, s::cl_uchar,
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_char, s::cl_char, s::cl_char,
s::cl_uchar)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_uchar, s::cl_uchar,
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_uchar, s::cl_uchar,
s::cl_uchar, s::cl_char)
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_uchar, s::cl_uchar,
s::cl_uchar, s::cl_uchar)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_short, s::cl_short,
s::cl_short, s::cl_short)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_short, s::cl_ushort,
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_short, s::cl_short,
s::cl_short, s::cl_short)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_ushort, s::cl_short,
s::cl_ushort, s::cl_ushort)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_ushort, s::cl_ushort,
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_short, s::cl_short,
s::cl_short, s::cl_ushort)
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_ushort, s::cl_ushort,
s::cl_ushort, s::cl_short)
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_ushort, s::cl_ushort,
s::cl_ushort, s::cl_ushort)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_int, s::cl_int, s::cl_int,
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_int, s::cl_int, s::cl_int,
s::cl_int)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_int, s::cl_uint, s::cl_int,
s::cl_int)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_uint, s::cl_int, s::cl_uint,
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_int, s::cl_int, s::cl_int,
s::cl_uint)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_uint, s::cl_uint, s::cl_uint,
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_uint, s::cl_uint, s::cl_uint,
s::cl_int)
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_uint, s::cl_uint, s::cl_uint,
s::cl_uint)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_long, s::cl_long, s::cl_long,
s::cl_long)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_long, s::cl_ulong, s::cl_long,
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_long, s::cl_long, s::cl_long,
s::cl_long)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_ulong, s::cl_long, s::cl_ulong,
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_long, s::cl_long, s::cl_long,
s::cl_ulong)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_ulong, s::cl_ulong,
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_ulong, s::cl_ulong,
s::cl_ulong, s::cl_long)
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_ulong, s::cl_ulong,
s::cl_ulong, s::cl_ulong)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_half, s::cl_short, s::cl_half,
s::cl_half)
MAKE_SC_FSC_1V_2V_3V_FV(Select, __vSelect, s::cl_half, s::cl_ushort, s::cl_half,
s::cl_half)
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_half, s::cl_half, s::cl_half,
s::cl_short)
MAKE_SC_FSC_1V_2V_3V_FV(select, __vselect, s::cl_half, s::cl_half, s::cl_half,
s::cl_ushort)
} // namespace __host_std
} // namespace cl
31 changes: 31 additions & 0 deletions sycl/test/built-ins/vector_relational.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@

#include <CL/sycl.hpp>

#include <iostream>
#include <cassert>
#include <cmath>

Expand Down Expand Up @@ -570,5 +571,35 @@ int main() {
assert(r4 == 34.34f);
}

{
s::vec<int, 4> r(0);
{
s::vec<int, 4> a(1, 2, 3, 4);
s::vec<int, 4> b(5, 6, 7, 8);
s::vec<unsigned int, 4> m(1u, 0x80000000u, 42u, 0x80001000u);
s::buffer<s::vec<int, 4>> A(&a, s::range<1>(1));
s::buffer<s::vec<int, 4>> B(&b, s::range<1>(1));
s::buffer<s::vec<unsigned int, 4>> M(&m, s::range<1>(1));
s::buffer<s::vec<int, 4>> R(&r, s::range<1>(1));
s::queue myQueue;
myQueue.submit([&](s::handler &cgh) {
auto AccA = A.get_access<s::access::mode::read>(cgh);
auto AccB = B.get_access<s::access::mode::read>(cgh);
auto AccM = M.get_access<s::access::mode::read>(cgh);
auto AccR = R.get_access<s::access::mode::write>(cgh);
cgh.single_task<class selectI4I4U4>([=]() {
AccR[0] = s::select(AccA[0], AccB[0], AccM[0]);
});
});
}
if (r.x() != 1 || r.y() != 6 || r.z() != 3 || r.w() != 8) {
std::cerr << "selectI4I4U4 test case failed!\n";
std::cerr << "Expected result: 1 6 3 8\n";
std::cerr << "Got: " << r.x() << " " << r.y() << " " << r.z() << " "
<< r.w() << "\n";
return 1;
}
}

return 0;
}