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Revert "[SystemZ] LivePhysRegs to LiveRegUnits (NFC) (#85162)"
This reverts commit 558c519. PR merged without review.
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llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
#include "SystemZInstrInfo.h"
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#include "SystemZSubtarget.h"
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#include "llvm/ADT/Statistic.h"
20-
#include "llvm/CodeGen/LiveRegUnits.h"
20+
#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
@@ -161,8 +161,7 @@ bool SystemZPostRewrite::expandCondMove(MachineBasicBlock &MBB,
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assert(DestReg == MI.getOperand(1).getReg() &&
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"Expected destination and first source operand to be the same.");
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164-
const TargetRegisterInfo &TRI = TII->getRegisterInfo();
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LiveRegUnits LiveRegs(TRI);
164+
LivePhysRegs LiveRegs(TII->getRegisterInfo());
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LiveRegs.addLiveOuts(MBB);
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for (auto I = std::prev(MBB.end()); I != MBBI; --I)
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LiveRegs.stepBackward(*I);
@@ -172,18 +171,15 @@ bool SystemZPostRewrite::expandCondMove(MachineBasicBlock &MBB,
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MF.insert(std::next(MachineFunction::iterator(MBB)), RestMBB);
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RestMBB->splice(RestMBB->begin(), &MBB, MI, MBB.end());
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RestMBB->transferSuccessors(&MBB);
175-
const BitVector &BV = TRI.getAllocatableSet(MF);
176-
for (Register Reg : BV.set_bits())
177-
if (!LiveRegs.available(Reg))
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RestMBB->addLiveIn(Reg);
174+
for (MCPhysReg R : LiveRegs)
175+
RestMBB->addLiveIn(R);
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// Create a new block MoveMBB to hold the move instruction.
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MachineBasicBlock *MoveMBB = MF.CreateMachineBasicBlock(BB);
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MF.insert(std::next(MachineFunction::iterator(MBB)), MoveMBB);
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MoveMBB->addLiveIn(SrcReg);
184-
for (Register Reg : BV.set_bits())
185-
if (!LiveRegs.available(Reg))
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MoveMBB->addLiveIn(Reg);
181+
for (MCPhysReg R : LiveRegs)
182+
MoveMBB->addLiveIn(R);
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// At the end of MBB, create a conditional branch to RestMBB if the
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// condition is false, otherwise fall through to MoveMBB.

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