[AArch64] Add FPAC to apple- processors that have it. #102072
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We added FPAC recently in d7e8a74 to allow ptrauth codegen to rely on the cpu auth failure checks rather than emitting its own auth failure check/brk sequence. Add it to the Apple processors that do have it: A15, A16, A17, M4. While there, tweak the description to refer to Armv8.3-A rather than v8.3-A, matching the other features.
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@llvm/pr-subscribers-backend-aarch64 @llvm/pr-subscribers-clang-driver Author: Ahmed Bougacha (ahmedbougacha) ChangesWe added FPAC recently in d7e8a74 to allow ptrauth codegen to rely on the cpu auth failure checks rather than emitting its own auth failure check/brk sequence. Add it to the Apple processors that do have it: A15, A16, A17, M4. While there, tweak the description to refer to Armv8.3-A rather than v8.3-A, matching the other features. Full diff: https://github.com/llvm/llvm-project/pull/102072.diff 7 Files Affected:
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c
index 267287eaf7b6e..dec48bb703311 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c
@@ -23,6 +23,7 @@
// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
index de382a3497b81..477652d83d82c 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
@@ -23,6 +23,7 @@
// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
index 641aa3f82387b..311cc94acddc9 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
@@ -23,6 +23,7 @@
// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
index 5096bc6940520..44d618afef406 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
@@ -23,6 +23,7 @@
// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index a1ae0873fc190..db0e1a2df16de 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -186,7 +186,7 @@ def FeatureJS : ExtensionWithMArch<"jsconv", "JS", "FEAT_JSCVT",
[FeatureFPARMv8]>;
def FeatureFPAC : Extension<"fpac", "FPAC", "FEAT_FPAC",
- "Enable v8.3-A Pointer Authentication Faulting enhancement">;
+ "Enable Armv8.3-A Pointer Authentication Faulting enhancement">;
def FeatureCCIDX : Extension<"ccidx", "CCIDX", "FEAT_CCIDX",
"Enable Armv8.3-A Extend of the CCSIDR number of sets">;
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index 71384a23c49af..52b5c8a0903ea 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -863,22 +863,25 @@ def ProcessorFeatures {
list<SubtargetFeature> AppleA15 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
- FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE,
- FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM,
+ FeatureComplxNum, FeatureCRC, FeatureJS,
+ FeatureLSE, FeaturePAuth, FeatureFPAC,
+ FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureBF16, FeatureDotProd, FeatureMatMulInt8];
list<SubtargetFeature> AppleA16 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
FeatureHCX,
- FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE,
- FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM,
+ FeatureComplxNum, FeatureCRC, FeatureJS,
+ FeatureLSE, FeaturePAuth, FeatureFPAC,
+ FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureBF16, FeatureDotProd, FeatureMatMulInt8];
list<SubtargetFeature> AppleA17 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
FeatureHCX,
- FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE,
- FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM,
+ FeatureComplxNum, FeatureCRC, FeatureJS,
+ FeatureLSE, FeaturePAuth, FeatureFPAC,
+ FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureBF16, FeatureDotProd, FeatureMatMulInt8];
list<SubtargetFeature> AppleM4 = [HasV9_2aOps, FeatureSHA2, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
@@ -886,8 +889,9 @@ def ProcessorFeatures {
FeatureAES, FeatureBF16,
FeatureSME, FeatureSME2,
FeatureSMEF64F64, FeatureSMEI16I64,
- FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE,
- FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM,
+ FeatureComplxNum, FeatureCRC, FeatureJS,
+ FeatureLSE, FeaturePAuth, FeatureFPAC,
+ FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureDotProd, FeatureMatMulInt8];
list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,
FeaturePerfMon, FeatureNEON, FeatureFPARMv8];
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 3d55b0309d26f..c6ea0b9900028 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1591,7 +1591,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}),
+ AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON}),
AArch64CPUTestParams(
"apple-m2", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
@@ -1600,7 +1600,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}),
+ AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON}),
AArch64CPUTestParams(
"apple-a16", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
@@ -1609,7 +1609,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_HCX}),
+ AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
+ AArch64::AEK_HCX}),
AArch64CPUTestParams(
"apple-m3", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
@@ -1618,7 +1619,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_HCX}),
+ AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
+ AArch64::AEK_HCX}),
AArch64CPUTestParams(
"apple-a17", "armv8.6-a",
{AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2,
@@ -1627,7 +1629,8 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
- AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_HCX}),
+ AArch64::AEK_PAUTH, AArch64::AEK_FPAC, AArch64::AEK_PERFMON,
+ AArch64::AEK_HCX}),
AArch64CPUTestParams("apple-m4", "armv9.2-a",
{AArch64::AEK_CRC, AArch64::AEK_AES,
AArch64::AEK_SHA2, AArch64::AEK_SHA3,
@@ -1637,10 +1640,10 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_DOTPROD, AArch64::AEK_FP16,
AArch64::AEK_FP16FML, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_JSCVT,
- AArch64::AEK_FCMA, AArch64::AEK_PAUTH,
+ AArch64::AEK_PAUTH, AArch64::AEK_FPAC,
+ AArch64::AEK_FCMA, AArch64::AEK_PERFMON,
AArch64::AEK_SME, AArch64::AEK_SME2,
- AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
- AArch64::AEK_PERFMON}),
+ AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64}),
AArch64CPUTestParams("exynos-m3", "armv8-a",
{AArch64::AEK_CRC, AArch64::AEK_AES,
AArch64::AEK_SHA2, AArch64::AEK_FP,
|
jroelofs
approved these changes
Aug 5, 2024
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We added FPAC recently in d7e8a74 to allow ptrauth codegen to rely on the cpu auth failure checks rather than emitting its own auth failure check/brk sequence.
Add it to the Apple processors that do have it: A15, A16, A17, M4.
While there, tweak the description to refer to Armv8.3-A rather than v8.3-A, matching the other features.