[RISCV] Remove RISCVISD::FP_EXTEND_BF16. #106939
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I don't think we need this node. We can isel fp_extend directly. fp_extend to f64 requires two instructions, but we can emit them with an isel pattern. I have not removed RISCVISD::FP_ROUND_BF16 because f64->bf16 needs more work to fix the double rounding.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesI don't think we need this node. We can isel fp_extend directly. fp_extend to f64 requires two instructions, but we can emit them with an isel pattern. I have not removed RISCVISD::FP_ROUND_BF16 because f64->bf16 needs more work to fix the double rounding. Full diff: https://github.com/llvm/llvm-project/pull/106939.diff 4 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d02078372b24a2..250d1c60b9f59e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -452,8 +452,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BITCAST, MVT::i16, Custom);
setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
setOperationAction(ISD::FP_ROUND, MVT::bf16, Custom);
- setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
- setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
setOperationAction(ISD::ConstantFP, MVT::bf16, Expand);
setOperationAction(ISD::SELECT_CC, MVT::bf16, Expand);
setOperationAction(ISD::BR_CC, MVT::bf16, Expand);
@@ -6500,18 +6498,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return SplitVectorOp(Op, DAG);
return lowerFMAXIMUM_FMINIMUM(Op, DAG, Subtarget);
case ISD::FP_EXTEND: {
- SDLoc DL(Op);
- EVT VT = Op.getValueType();
- SDValue Op0 = Op.getOperand(0);
- EVT Op0VT = Op0.getValueType();
- if (VT == MVT::f32 && Op0VT == MVT::bf16 && Subtarget.hasStdExtZfbfmin())
- return DAG.getNode(RISCVISD::FP_EXTEND_BF16, DL, MVT::f32, Op0);
- if (VT == MVT::f64 && Op0VT == MVT::bf16 && Subtarget.hasStdExtZfbfmin()) {
- SDValue FloatVal =
- DAG.getNode(RISCVISD::FP_EXTEND_BF16, DL, MVT::f32, Op0);
- return DAG.getNode(ISD::FP_EXTEND, DL, MVT::f64, FloatVal);
- }
-
if (!Op.getValueType().isVector())
return Op;
return lowerVectorFPExtendOrRoundLike(Op, DAG);
@@ -20463,7 +20449,6 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(STRICT_FCVT_W_RV64)
NODE_NAME_CASE(STRICT_FCVT_WU_RV64)
NODE_NAME_CASE(FP_ROUND_BF16)
- NODE_NAME_CASE(FP_EXTEND_BF16)
NODE_NAME_CASE(FROUND)
NODE_NAME_CASE(FCLASS)
NODE_NAME_CASE(FSGNJX)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 9ae35173ba0cb3..29a16282ed001d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -117,7 +117,6 @@ enum NodeType : unsigned {
FCVT_WU_RV64,
FP_ROUND_BF16,
- FP_EXTEND_BF16,
// Rounds an FP value to its corresponding integer in the same FP format.
// First operand is the value to round, the second operand is the largest
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 0f435c4ff3d315..7f9ca02fad43f9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -1294,7 +1294,7 @@ defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACC",
fpext_oneuse>;
defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACCBF16",
AllWidenableBFloatToFloatVectors,
- riscv_fpextend_bf16_oneuse>;
+ fpext_oneuse>;
defm : VPatWidenFPNegMulAccSDNode_VV_VF_RM<"PseudoVFWNMACC">;
defm : VPatWidenFPMulSacSDNode_VV_VF_RM<"PseudoVFWMSAC">;
defm : VPatWidenFPNegMulSacSDNode_VV_VF_RM<"PseudoVFWNMSAC">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
index 88b66e7fc49aad..bf6272317fda4d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
@@ -19,17 +19,9 @@
def SDT_RISCVFP_ROUND_BF16
: SDTypeProfile<1, 1, [SDTCisVT<0, bf16>, SDTCisVT<1, f32>]>;
-def SDT_RISCVFP_EXTEND_BF16
- : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, bf16>]>;
def riscv_fpround_bf16
: SDNode<"RISCVISD::FP_ROUND_BF16", SDT_RISCVFP_ROUND_BF16>;
-def riscv_fpextend_bf16
- : SDNode<"RISCVISD::FP_EXTEND_BF16", SDT_RISCVFP_EXTEND_BF16>;
-def riscv_fpextend_bf16_oneuse : PatFrag<(ops node:$A),
- (riscv_fpextend_bf16 node:$A), [{
- return N->hasOneUse();
-}]>;
//===----------------------------------------------------------------------===//
// Instructions
@@ -57,7 +49,7 @@ def : StPat<store, FSH, FPR16, bf16>;
// f32 -> bf16, bf16 -> f32
def : Pat<(bf16 (riscv_fpround_bf16 FPR32:$rs1)),
(FCVT_BF16_S FPR32:$rs1, FRM_DYN)>;
-def : Pat<(riscv_fpextend_bf16 (bf16 FPR16:$rs1)),
+def : Pat<(fpextend (bf16 FPR16:$rs1)),
(FCVT_S_BF16 FPR16:$rs1, FRM_DYN)>;
// Moves (no conversion)
@@ -87,3 +79,9 @@ def : Pat<(i64 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_BF16 $rs1
def : Pat<(bf16 (any_sint_to_fp (i64 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_L $rs1, FRM_DYN), FRM_DYN)>;
def : Pat<(bf16 (any_uint_to_fp (i64 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_LU $rs1, FRM_DYN), FRM_DYN)>;
}
+
+let Predicates = [HasStdExtZfbfmin, HasStdExtD] in {
+// bf16 -> f64
+def : Pat<(fpextend (bf16 FPR16:$rs1)),
+ (FCVT_D_S (FCVT_S_BF16 FPR16:$rs1, FRM_DYN), FRM_RNE)>;
+}
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lukel97
reviewed
Sep 2, 2024
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/162/builds/5368 Here is the relevant piece of the build log for the reference |
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I don't think we need this node. We can isel fp_extend directly. fp_extend to f64 requires two instructions, but we can emit them with an isel pattern.
I have not removed RISCVISD::FP_ROUND_BF16 because f64->bf16 needs more work to fix the double rounding.