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[RISCV] Remove RISCVISD::FP_EXTEND_BF16. #106939

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Merged
merged 2 commits into from
Sep 2, 2024
Merged

[RISCV] Remove RISCVISD::FP_EXTEND_BF16. #106939

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d0f2613
[RISCV] Remove RISCVISD::FP_EXTEND_BF16.
topperc Sep 2, 2024
13d779f
fixup! address review comment
topperc Sep 2, 2024
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15 changes: 0 additions & 15 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -452,8 +452,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BITCAST, MVT::i16, Custom);
setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
setOperationAction(ISD::FP_ROUND, MVT::bf16, Custom);
setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
setOperationAction(ISD::ConstantFP, MVT::bf16, Expand);
setOperationAction(ISD::SELECT_CC, MVT::bf16, Expand);
setOperationAction(ISD::BR_CC, MVT::bf16, Expand);
Expand Down Expand Up @@ -6500,18 +6498,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return SplitVectorOp(Op, DAG);
return lowerFMAXIMUM_FMINIMUM(Op, DAG, Subtarget);
case ISD::FP_EXTEND: {
SDLoc DL(Op);
EVT VT = Op.getValueType();
SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType();
if (VT == MVT::f32 && Op0VT == MVT::bf16 && Subtarget.hasStdExtZfbfmin())
return DAG.getNode(RISCVISD::FP_EXTEND_BF16, DL, MVT::f32, Op0);
if (VT == MVT::f64 && Op0VT == MVT::bf16 && Subtarget.hasStdExtZfbfmin()) {
SDValue FloatVal =
DAG.getNode(RISCVISD::FP_EXTEND_BF16, DL, MVT::f32, Op0);
return DAG.getNode(ISD::FP_EXTEND, DL, MVT::f64, FloatVal);
}

if (!Op.getValueType().isVector())
return Op;
return lowerVectorFPExtendOrRoundLike(Op, DAG);
Expand Down Expand Up @@ -20463,7 +20449,6 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(STRICT_FCVT_W_RV64)
NODE_NAME_CASE(STRICT_FCVT_WU_RV64)
NODE_NAME_CASE(FP_ROUND_BF16)
NODE_NAME_CASE(FP_EXTEND_BF16)
NODE_NAME_CASE(FROUND)
NODE_NAME_CASE(FCLASS)
NODE_NAME_CASE(FSGNJX)
Expand Down
1 change: 0 additions & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.h
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Expand Up @@ -117,7 +117,6 @@ enum NodeType : unsigned {
FCVT_WU_RV64,

FP_ROUND_BF16,
FP_EXTEND_BF16,

// Rounds an FP value to its corresponding integer in the same FP format.
// First operand is the value to round, the second operand is the largest
Expand Down
11 changes: 4 additions & 7 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
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Expand Up @@ -677,8 +677,7 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_WV_WF_RM<SDNode op,
VPatWidenBinaryFPSDNode_WV_WF_RM<op, instruction_name>;

multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name,
list <VTypeInfoToWide> vtiToWtis,
PatFrags extop> {
list <VTypeInfoToWide> vtiToWtis> {
foreach vtiToWti = vtiToWtis in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
Expand All @@ -702,7 +701,7 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name,
FRM_DYN,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (SplatFPOp
(extop (vti.Scalar vti.ScalarRegClass:$rs1)))),
(fpext_oneuse (vti.Scalar vti.ScalarRegClass:$rs1)))),
(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
Expand Down Expand Up @@ -1290,11 +1289,9 @@ foreach fvti = AllFloatVectors in {

// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACC",
AllWidenableFloatVectors,
fpext_oneuse>;
AllWidenableFloatVectors>;
defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACCBF16",
AllWidenableBFloatToFloatVectors,
riscv_fpextend_bf16_oneuse>;
AllWidenableBFloatToFloatVectors>;
defm : VPatWidenFPNegMulAccSDNode_VV_VF_RM<"PseudoVFWNMACC">;
defm : VPatWidenFPMulSacSDNode_VV_VF_RM<"PseudoVFWMSAC">;
defm : VPatWidenFPNegMulSacSDNode_VV_VF_RM<"PseudoVFWNMSAC">;
Expand Down
16 changes: 7 additions & 9 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
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Expand Up @@ -19,17 +19,9 @@

def SDT_RISCVFP_ROUND_BF16
: SDTypeProfile<1, 1, [SDTCisVT<0, bf16>, SDTCisVT<1, f32>]>;
def SDT_RISCVFP_EXTEND_BF16
: SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, bf16>]>;

def riscv_fpround_bf16
: SDNode<"RISCVISD::FP_ROUND_BF16", SDT_RISCVFP_ROUND_BF16>;
def riscv_fpextend_bf16
: SDNode<"RISCVISD::FP_EXTEND_BF16", SDT_RISCVFP_EXTEND_BF16>;
def riscv_fpextend_bf16_oneuse : PatFrag<(ops node:$A),
(riscv_fpextend_bf16 node:$A), [{
return N->hasOneUse();
}]>;

//===----------------------------------------------------------------------===//
// Instructions
Expand Down Expand Up @@ -57,7 +49,7 @@ def : StPat<store, FSH, FPR16, bf16>;
// f32 -> bf16, bf16 -> f32
def : Pat<(bf16 (riscv_fpround_bf16 FPR32:$rs1)),
(FCVT_BF16_S FPR32:$rs1, FRM_DYN)>;
def : Pat<(riscv_fpextend_bf16 (bf16 FPR16:$rs1)),
def : Pat<(fpextend (bf16 FPR16:$rs1)),
(FCVT_S_BF16 FPR16:$rs1, FRM_DYN)>;

// Moves (no conversion)
Expand Down Expand Up @@ -87,3 +79,9 @@ def : Pat<(i64 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_BF16 $rs1
def : Pat<(bf16 (any_sint_to_fp (i64 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_L $rs1, FRM_DYN), FRM_DYN)>;
def : Pat<(bf16 (any_uint_to_fp (i64 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_LU $rs1, FRM_DYN), FRM_DYN)>;
}

let Predicates = [HasStdExtZfbfmin, HasStdExtD] in {
// bf16 -> f64
def : Pat<(fpextend (bf16 FPR16:$rs1)),
(FCVT_D_S (FCVT_S_BF16 FPR16:$rs1, FRM_DYN), FRM_RNE)>;
}
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