[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. #106967

cdevadas · 2024-09-02T10:33:27Z

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cdevadas · 2024-09-02T10:33:44Z

[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. #106967 👈
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llvmbot · 2024-09-02T10:36:50Z

@llvm/pr-subscribers-backend-amdgpu

Author: Christudasan Devadasan (cdevadas)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/106967.diff

17 Files Affected:

(modified) llvm/lib/Target/AMDGPU/AMDGPU.h (+3-3)
(modified) llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def (+1)
(modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+4-3)
(modified) llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp (+37-15)
(added) llvm/lib/Target/AMDGPU/SIShrinkInstructions.h (+25)
(modified) llvm/test/CodeGen/AMDGPU/cmp_shrink.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/fold-multiple.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/shrink-true16.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/v_swap_b32.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir (+1)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 6cc6863841a4c5..8d6e022e1e4d42 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -39,7 +39,7 @@ FunctionPass *createSIFoldOperandsLegacyPass();
 FunctionPass *createSIPeepholeSDWAPass();
 FunctionPass *createSILowerI1CopiesLegacyPass();
 FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
-FunctionPass *createSIShrinkInstructionsPass();
+FunctionPass *createSIShrinkInstructionsLegacyPass();
 FunctionPass *createSILoadStoreOptimizerLegacyPass();
 FunctionPass *createSIWholeQuadModePass();
 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
@@ -166,8 +166,8 @@ extern char &SIFoldOperandsLegacyID;
 void initializeSIPeepholeSDWAPass(PassRegistry &);
 extern char &SIPeepholeSDWAID;
 
-void initializeSIShrinkInstructionsPass(PassRegistry&);
-extern char &SIShrinkInstructionsID;
+void initializeSIShrinkInstructionsLegacyPass(PassRegistry &);
+extern char &SIShrinkInstructionsLegacyID;
 
 void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &);
 extern char &SIFixSGPRCopiesLegacyID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index d01e3f0b97ddd1..58481fe9df239f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -100,4 +100,5 @@ MACHINE_FUNCTION_PASS("si-i1-copies", SILowerI1CopiesPass())
 MACHINE_FUNCTION_PASS("si-fold-operands", SIFoldOperandsPass());
 MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass())
 MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
+MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
 #undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 757a575841e61a..18e466d2bd5b5b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -39,6 +39,7 @@
 #include "SILoadStoreOptimizer.h"
 #include "SIMachineFunctionInfo.h"
 #include "SIMachineScheduler.h"
+#include "SIShrinkInstructions.h"
 #include "TargetInfo/AMDGPUTargetInfo.h"
 #include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/Analysis/CGSCCPassManager.h"
@@ -415,7 +416,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
   initializeSIFixVGPRCopiesPass(*PR);
   initializeSIFoldOperandsLegacyPass(*PR);
   initializeSIPeepholeSDWAPass(*PR);
-  initializeSIShrinkInstructionsPass(*PR);
+  initializeSIShrinkInstructionsLegacyPass(*PR);
   initializeSIOptimizeExecMaskingPreRAPass(*PR);
   initializeSIOptimizeVGPRLiveRangePass(*PR);
   initializeSILoadStoreOptimizerLegacyPass(*PR);
@@ -1280,7 +1281,7 @@ void GCNPassConfig::addMachineSSAOptimization() {
     addPass(&SIFoldOperandsLegacyID);
   }
   addPass(&DeadMachineInstructionElimID);
-  addPass(createSIShrinkInstructionsPass());
+  addPass(createSIShrinkInstructionsLegacyPass());
 }
 
 bool GCNPassConfig::addILPOpts() {
@@ -1484,7 +1485,7 @@ void GCNPassConfig::addPostRegAlloc() {
 
 void GCNPassConfig::addPreSched2() {
   if (TM->getOptLevel() > CodeGenOptLevel::None)
-    addPass(createSIShrinkInstructionsPass());
+    addPass(createSIShrinkInstructionsLegacyPass());
   addPass(&SIPostRABundlerID);
 }
 
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 6e945bf368f4eb..9967a65244413a 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -8,6 +8,7 @@
 //===----------------------------------------------------------------------===//
 //
 
+#include "SIShrinkInstructions.h"
 #include "AMDGPU.h"
 #include "GCNSubtarget.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -26,20 +27,13 @@ using namespace llvm;
 
 namespace {
 
-class SIShrinkInstructions : public MachineFunctionPass {
+class SIShrinkInstructions {
   MachineFunction *MF;
   MachineRegisterInfo *MRI;
   const GCNSubtarget *ST;
   const SIInstrInfo *TII;
   const SIRegisterInfo *TRI;
 
-public:
-  static char ID;
-
-public:
-  SIShrinkInstructions() : MachineFunctionPass(ID) {
-  }
-
   bool foldImmediates(MachineInstr &MI, bool TryToCommute = true) const;
   bool shouldShrinkTrue16(MachineInstr &MI) const;
   bool isKImmOperand(const MachineOperand &Src) const;
@@ -62,6 +56,18 @@ class SIShrinkInstructions : public MachineFunctionPass {
   void dropInstructionKeepingImpDefs(MachineInstr &MI) const;
   MachineInstr *matchSwap(MachineInstr &MovT) const;
 
+public:
+  SIShrinkInstructions() = default;
+  bool run(MachineFunction &MF);
+};
+
+class SIShrinkInstructionsLegacy : public MachineFunctionPass {
+
+public:
+  static char ID;
+
+  SIShrinkInstructionsLegacy() : MachineFunctionPass(ID) {}
+
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   StringRef getPassName() const override { return "SI Shrink Instructions"; }
@@ -74,13 +80,13 @@ class SIShrinkInstructions : public MachineFunctionPass {
 
 } // End anonymous namespace.
 
-INITIALIZE_PASS(SIShrinkInstructions, DEBUG_TYPE,
+INITIALIZE_PASS(SIShrinkInstructionsLegacy, DEBUG_TYPE,
                 "SI Shrink Instructions", false, false)
 
-char SIShrinkInstructions::ID = 0;
+char SIShrinkInstructionsLegacy::ID = 0;
 
-FunctionPass *llvm::createSIShrinkInstructionsPass() {
-  return new SIShrinkInstructions();
+FunctionPass *llvm::createSIShrinkInstructionsLegacyPass() {
+  return new SIShrinkInstructionsLegacy();
 }
 
 /// This function checks \p MI for operands defined by a move immediate
@@ -815,9 +821,7 @@ bool SIShrinkInstructions::tryReplaceDeadSDST(MachineInstr &MI) const {
   return true;
 }
 
-bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
-  if (skipFunction(MF.getFunction()))
-    return false;
+bool SIShrinkInstructions::run(MachineFunction &MF) {
 
   this->MF = &MF;
   MRI = &MF.getRegInfo();
@@ -1077,3 +1081,21 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
   }
   return false;
 }
+
+bool SIShrinkInstructionsLegacy::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(MF.getFunction()))
+    return false;
+
+  return SIShrinkInstructions().run(MF);
+}
+
+PreservedAnalyses
+SIShrinkInstructionsPass::run(MachineFunction &MF,
+                              MachineFunctionAnalysisManager &) {
+  if (MF.getFunction().hasOptNone() || !SIShrinkInstructions().run(MF))
+    return PreservedAnalyses::all();
+
+  auto PA = getMachineFunctionPassPreservedAnalyses();
+  PA.preserveSet<CFGAnalyses>();
+  return PA;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.h b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.h
new file mode 100644
index 00000000000000..7fc99ea65d2858
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.h
@@ -0,0 +1,25 @@
+//===- SIShrinkInstructions.h -----------------------------------*- C++- *-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_SISHRINKINSTRUCTIONS_H
+#define LLVM_LIB_TARGET_AMDGPU_SISHRINKINSTRUCTIONS_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class SIShrinkInstructionsPass
+    : public PassInfoMixin<SIShrinkInstructionsPass> {
+public:
+  SIShrinkInstructionsPass() = default;
+  PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &);
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_AMDGPU_SISHRINKINSTRUCTIONS_H
diff --git a/llvm/test/CodeGen/AMDGPU/cmp_shrink.mir b/llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
index 6750f6430f71f7..9b3579b43a38a3 100644
--- a/llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
+++ b/llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
 
 ---
 name:             not_shrink_icmp
diff --git a/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir b/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
index dd61d9cf4bb2db..919641f7e70d37 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
@@ -1,4 +1,5 @@
 # RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
+# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -passes si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
 --- |
   define amdgpu_kernel void @add_f32_1.0_one_f16_use() #0 {
     %f16.val0 = load volatile half, ptr addrspace(1) undef
diff --git a/llvm/test/CodeGen/AMDGPU/fold-multiple.mir b/llvm/test/CodeGen/AMDGPU/fold-multiple.mir
index d0d8542d1a1b24..9d992da0797755 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-multiple.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-multiple.mir
@@ -1,4 +1,5 @@
 # RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
+# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -passes si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
 --- |
   define amdgpu_kernel void @test() #0 {
     ret void
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir b/llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
index 764ac91a9049c9..83adb93c9f41e6 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
 # RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -passes=si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
 
 ---
 name:            shrink_kimm32_mov_b32
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir b/llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
index 37d7a758d6fd7f..d63be9ccea611f 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -run-pass=si-shrink-instructions %s -o - | FileCheck %s
+# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -passes=si-shrink-instructions %s -o - | FileCheck %s
 
 # Make sure flags are preserved when shrinking instructions
 ---
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir b/llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
index 7cebd0e796aae9..6f5aa70649beee 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-instructions-illegal-fold.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-shrink-instructions --verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=si-shrink-instructions --verify-machineinstrs %s -o - | FileCheck %s
 
 # Make sure immediate folding into V_CNDMASK respects constant bus restrictions.
 ---
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir b/llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
index eb7b9b619ee006..a8deda7ad95078 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck %s
 
 ---
 name:            undef_and_operand_to_bitset0
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-true16.mir b/llvm/test/CodeGen/AMDGPU/shrink-true16.mir
index 4b2e3951ce4c13..1a7ec5db9efa2a 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-true16.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-true16.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1100 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1100 %s
 
 ---
 name: 16bit_lo128_shrink
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
index 8b2f659c7d4ba6..9c74d94a1afefe 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
@@ -1,4 +1,5 @@
 # RUN: llc -verify-machineinstrs -mtriple=amdgcn -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -verify-machineinstrs -mtriple=amdgcn -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
 # Check that add with carry out isn't incorrectly reduced to e32 when
 # the carry out is a virtual register.
 
diff --git a/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir b/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
index 5a942bd505300f..95aaea6ea80913 100644
--- a/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
+++ b/llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
@@ -1,4 +1,5 @@
 # RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx900 -passes=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
 
 # GCN-LABEL: name: swap_phys_condensed
 # GCN: bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir b/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
index c5d3acf1009906..7c032c2dc49724 100644
--- a/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
+++ b/llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
 --- |
 
   define amdgpu_kernel void @fold_fi_vgpr() {
diff --git a/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir b/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
index 992378a6336a68..292e96b4516fec 100644
--- a/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
+++ b/llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
 ...
 # GCN-LABEL: name: fold_imm_non_ssa{{$}}
 # GCN: %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec

pravinjagtap

LGTM

pravinjagtap · 2024-09-02T15:06:12Z

llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

+PreservedAnalyses
+SIShrinkInstructionsPass::run(MachineFunction &MF,
+                              MachineFunctionAnalysisManager &) {
+  if (MF.getFunction().hasOptNone() || !SIShrinkInstructions().run(MF))


Shouldn't codegen pipeline builder take care of opt none? I am not sure when to use TM and Fcn attribute to decide pass invocatoin.

This early exit is mainly to skip the optimization passes for -O0. This specific check hasOptNone checks for the function attribute Attribute::OptimizeNone, set to true for -O0 opt.levels. The attributes and metadata are still in the LLVM IR and not available in the MIR.

cdevadas · 2024-09-03T05:21:07Z

Merge activity

Sep 3, 1:21 AM EDT: @cdevadas started a stack merge that includes this pull request via Graphite.
Sep 3, 1:22 AM EDT: @cdevadas merged this pull request with Graphite.

[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager.

4ef20b6

cdevadas requested review from optimisan, arsenm and pravinjagtap September 2, 2024 10:36

cdevadas marked this pull request as ready for review September 2, 2024 10:36

llvmbot added the backend:AMDGPU label Sep 2, 2024

pravinjagtap reviewed Sep 2, 2024

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pravinjagtap approved these changes Sep 2, 2024

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cdevadas merged commit 0421049 into main Sep 3, 2024
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cdevadas deleted the users/cdevadas/port-sishrink-instr-pass branch September 3, 2024 05:22

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