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[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. #106967

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6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPU.h
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ FunctionPass *createSIFoldOperandsLegacyPass();
FunctionPass *createSIPeepholeSDWAPass();
FunctionPass *createSILowerI1CopiesLegacyPass();
FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
FunctionPass *createSIShrinkInstructionsPass();
FunctionPass *createSIShrinkInstructionsLegacyPass();
FunctionPass *createSILoadStoreOptimizerLegacyPass();
FunctionPass *createSIWholeQuadModePass();
FunctionPass *createSIFixControlFlowLiveIntervalsPass();
Expand Down Expand Up @@ -166,8 +166,8 @@ extern char &SIFoldOperandsLegacyID;
void initializeSIPeepholeSDWAPass(PassRegistry &);
extern char &SIPeepholeSDWAID;

void initializeSIShrinkInstructionsPass(PassRegistry&);
extern char &SIShrinkInstructionsID;
void initializeSIShrinkInstructionsLegacyPass(PassRegistry &);
extern char &SIShrinkInstructionsLegacyID;

void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &);
extern char &SIFixSGPRCopiesLegacyID;
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
Original file line number Diff line number Diff line change
Expand Up @@ -100,4 +100,5 @@ MACHINE_FUNCTION_PASS("si-i1-copies", SILowerI1CopiesPass())
MACHINE_FUNCTION_PASS("si-fold-operands", SIFoldOperandsPass());
MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
#undef MACHINE_FUNCTION_PASS
7 changes: 4 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,7 @@
#include "SILoadStoreOptimizer.h"
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIShrinkInstructions.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/Analysis/CGSCCPassManager.h"
Expand Down Expand Up @@ -415,7 +416,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeSIFixVGPRCopiesPass(*PR);
initializeSIFoldOperandsLegacyPass(*PR);
initializeSIPeepholeSDWAPass(*PR);
initializeSIShrinkInstructionsPass(*PR);
initializeSIShrinkInstructionsLegacyPass(*PR);
initializeSIOptimizeExecMaskingPreRAPass(*PR);
initializeSIOptimizeVGPRLiveRangePass(*PR);
initializeSILoadStoreOptimizerLegacyPass(*PR);
Expand Down Expand Up @@ -1280,7 +1281,7 @@ void GCNPassConfig::addMachineSSAOptimization() {
addPass(&SIFoldOperandsLegacyID);
}
addPass(&DeadMachineInstructionElimID);
addPass(createSIShrinkInstructionsPass());
addPass(createSIShrinkInstructionsLegacyPass());
}

bool GCNPassConfig::addILPOpts() {
Expand Down Expand Up @@ -1484,7 +1485,7 @@ void GCNPassConfig::addPostRegAlloc() {

void GCNPassConfig::addPreSched2() {
if (TM->getOptLevel() > CodeGenOptLevel::None)
addPass(createSIShrinkInstructionsPass());
addPass(createSIShrinkInstructionsLegacyPass());
addPass(&SIPostRABundlerID);
}

Expand Down
52 changes: 37 additions & 15 deletions llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
//===----------------------------------------------------------------------===//
//

#include "SIShrinkInstructions.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
Expand All @@ -26,20 +27,13 @@ using namespace llvm;

namespace {

class SIShrinkInstructions : public MachineFunctionPass {
class SIShrinkInstructions {
MachineFunction *MF;
MachineRegisterInfo *MRI;
const GCNSubtarget *ST;
const SIInstrInfo *TII;
const SIRegisterInfo *TRI;

public:
static char ID;

public:
SIShrinkInstructions() : MachineFunctionPass(ID) {
}

bool foldImmediates(MachineInstr &MI, bool TryToCommute = true) const;
bool shouldShrinkTrue16(MachineInstr &MI) const;
bool isKImmOperand(const MachineOperand &Src) const;
Expand All @@ -62,6 +56,18 @@ class SIShrinkInstructions : public MachineFunctionPass {
void dropInstructionKeepingImpDefs(MachineInstr &MI) const;
MachineInstr *matchSwap(MachineInstr &MovT) const;

public:
SIShrinkInstructions() = default;
bool run(MachineFunction &MF);
};

class SIShrinkInstructionsLegacy : public MachineFunctionPass {

public:
static char ID;

SIShrinkInstructionsLegacy() : MachineFunctionPass(ID) {}

bool runOnMachineFunction(MachineFunction &MF) override;

StringRef getPassName() const override { return "SI Shrink Instructions"; }
Expand All @@ -74,13 +80,13 @@ class SIShrinkInstructions : public MachineFunctionPass {

} // End anonymous namespace.

INITIALIZE_PASS(SIShrinkInstructions, DEBUG_TYPE,
INITIALIZE_PASS(SIShrinkInstructionsLegacy, DEBUG_TYPE,
"SI Shrink Instructions", false, false)

char SIShrinkInstructions::ID = 0;
char SIShrinkInstructionsLegacy::ID = 0;

FunctionPass *llvm::createSIShrinkInstructionsPass() {
return new SIShrinkInstructions();
FunctionPass *llvm::createSIShrinkInstructionsLegacyPass() {
return new SIShrinkInstructionsLegacy();
}

/// This function checks \p MI for operands defined by a move immediate
Expand Down Expand Up @@ -815,9 +821,7 @@ bool SIShrinkInstructions::tryReplaceDeadSDST(MachineInstr &MI) const {
return true;
}

bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
bool SIShrinkInstructions::run(MachineFunction &MF) {

this->MF = &MF;
MRI = &MF.getRegInfo();
Expand Down Expand Up @@ -1077,3 +1081,21 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
}
return false;
}

bool SIShrinkInstructionsLegacy::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;

return SIShrinkInstructions().run(MF);
}

PreservedAnalyses
SIShrinkInstructionsPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &) {
if (MF.getFunction().hasOptNone() || !SIShrinkInstructions().run(MF))
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Shouldn't codegen pipeline builder take care of opt none? I am not sure when to use TM and Fcn attribute to decide pass invocatoin.

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This early exit is mainly to skip the optimization passes for -O0. This specific check hasOptNone checks for the function attribute Attribute::OptimizeNone, set to true for -O0 opt.levels. The attributes and metadata are still in the LLVM IR and not available in the MIR.

return PreservedAnalyses::all();

auto PA = getMachineFunctionPassPreservedAnalyses();
PA.preserveSet<CFGAnalyses>();
return PA;
}
25 changes: 25 additions & 0 deletions llvm/lib/Target/AMDGPU/SIShrinkInstructions.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
//===- SIShrinkInstructions.h -----------------------------------*- C++- *-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_AMDGPU_SISHRINKINSTRUCTIONS_H
#define LLVM_LIB_TARGET_AMDGPU_SISHRINKINSTRUCTIONS_H

#include "llvm/CodeGen/MachinePassManager.h"

namespace llvm {

class SIShrinkInstructionsPass
: public PassInfoMixin<SIShrinkInstructionsPass> {
public:
SIShrinkInstructionsPass() = default;
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &);
};

} // namespace llvm

#endif // LLVM_LIB_TARGET_AMDGPU_SISHRINKINSTRUCTIONS_H
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s

---
name: not_shrink_icmp
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -passes si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
--- |
define amdgpu_kernel void @add_f32_1.0_one_f16_use() #0 {
%f16.val0 = load volatile half, ptr addrspace(1) undef
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/fold-multiple.mir
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -passes si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
--- |
define amdgpu_kernel void @test() #0 {
ret void
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/shrink-i32-kimm.mir
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -passes=si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s

---
name: shrink_kimm32_mov_b32
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -run-pass=si-shrink-instructions %s -o - | FileCheck %s
# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -passes=si-shrink-instructions %s -o - | FileCheck %s

# Make sure flags are preserved when shrinking instructions
---
Expand Down
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-shrink-instructions --verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=si-shrink-instructions --verify-machineinstrs %s -o - | FileCheck %s

# Make sure immediate folding into V_CNDMASK respects constant bus restrictions.
---
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck %s

---
name: undef_and_operand_to_bitset0
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/shrink-true16.mir
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1100 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1100 %s

---
name: 16bit_lo128_shrink
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
# RUN: llc -verify-machineinstrs -mtriple=amdgcn -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -verify-machineinstrs -mtriple=amdgcn -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
# Check that add with carry out isn't incorrectly reduced to e32 when
# the carry out is a virtual register.

Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx900 -passes=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s

# GCN-LABEL: name: swap_phys_condensed
# GCN: bb.0:
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
--- |

define amdgpu_kernel void @fold_fi_vgpr() {
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -passes si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
...
# GCN-LABEL: name: fold_imm_non_ssa{{$}}
# GCN: %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
Expand Down
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