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[RISCV] Enable floating point CSR alias mnemonics for Zfinx. #108464

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Merged
merged 2 commits into from
Sep 13, 2024
Merged

[RISCV] Enable floating point CSR alias mnemonics for Zfinx. #108464

merged 2 commits into from
Sep 13, 2024

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@topperc topperc commented Sep 12, 2024

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@llvmbot llvmbot added backend:RISC-V mc Machine (object) code labels Sep 12, 2024
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llvmbot commented Sep 12, 2024 •
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@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-mc

Author: Craig Topper (topperc)

Changes

Patch is 35.38 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/108464.diff

8 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+5)
  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfoF.td (+17-15)
  • (modified) llvm/test/CodeGen/RISCV/double-fcmp-strict.ll (+48-48)
  • (modified) llvm/test/CodeGen/RISCV/float-fcmp-strict.ll (+24-24)
  • (modified) llvm/test/CodeGen/RISCV/half-fcmp-strict.ll (+48-48)
  • (modified) llvm/test/MC/RISCV/csr-aliases.s (+6)
  • (modified) llvm/test/MC/RISCV/rvf-aliases-valid.s (+2-1)
  • (modified) llvm/test/MC/RISCV/rvzfinx-aliases-valid.s (+61-4)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fa141c31f94dbd..c802274aa78c32 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -348,6 +348,11 @@ def FeatureStdExtZfinx
 def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
                      AssemblerPredicate<(all_of FeatureStdExtZfinx),
                                         "'Zfinx' (Float in Integer)">;
+def HasStdExtFOrZfinx : Predicate<"Subtarget->hasStdExtFOrZfinx()">,
+                        AssemblerPredicate<(any_of FeatureStdExtF,
+                                                   FeatureStdExtZfinx),
+                            "'F' (Single-Precision Floating-Point) or "
+                            "'Zfinx' (Float in Integer)">;
 
 def FeatureStdExtZdinx
     : RISCVExtension<"zdinx", 1, 0,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 1442bc1cbc4feb..d22ed37e8cca87 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -400,21 +400,7 @@ def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasStdExtF] in {
-def : InstAlias<"flw $rd, (${rs1})",  (FLW FPR32:$rd,  GPR:$rs1, 0), 0>;
-def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
-
-def : InstAlias<"fmv.s $rd, $rs",  (FSGNJ_S  FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
-def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
-def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
-
-// fgt.s/fge.s are recognised by the GNU assembler but the canonical
-// flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
-def : InstAlias<"fgt.s $rd, $rs, $rt",
-                (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
-def : InstAlias<"fge.s $rd, $rs, $rt",
-                (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
-
+let Predicates = [HasStdExtFOrZfinx] in {
 // The following csr instructions actually alias instructions from the base ISA.
 // However, it only makes sense to support them when the F extension is enabled.
 // NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr".
@@ -439,6 +425,22 @@ def : InstAlias<"fsflags $rd, $rs",   (CSRRW  GPR:$rd, SysRegFFLAGS.Encoding, GP
 def : InstAlias<"fsflags $rs",        (CSRRW       X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>;
 def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>;
 def : InstAlias<"fsflagsi $imm",      (CSRRWI      X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>;
+} // Predicates = [HasStdExtFOrZfinx]
+
+let Predicates = [HasStdExtF] in {
+def : InstAlias<"flw $rd, (${rs1})",  (FLW FPR32:$rd,  GPR:$rs1, 0), 0>;
+def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
+
+def : InstAlias<"fmv.s $rd, $rs",  (FSGNJ_S  FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
+def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
+def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
+
+// fgt.s/fge.s are recognised by the GNU assembler but the canonical
+// flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
+def : InstAlias<"fgt.s $rd, $rs, $rt",
+                (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
+def : InstAlias<"fge.s $rd, $rs, $rt",
+                (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
 
 // fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both
 // spellings should be supported by standard tools.
diff --git a/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
index e864d8fb0eddd5..949668f640dbd2 100644
--- a/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
@@ -68,18 +68,18 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind strictfp {
 ;
 ; RV32IZFINXZDINX-LABEL: fcmp_ogt:
 ; RV32IZFINXZDINX:       # %bb.0:
-; RV32IZFINXZDINX-NEXT:    csrr a5, fflags
+; RV32IZFINXZDINX-NEXT:    frflags a5
 ; RV32IZFINXZDINX-NEXT:    flt.d a4, a2, a0
-; RV32IZFINXZDINX-NEXT:    csrw fflags, a5
+; RV32IZFINXZDINX-NEXT:    fsflags a5
 ; RV32IZFINXZDINX-NEXT:    feq.d zero, a2, a0
 ; RV32IZFINXZDINX-NEXT:    mv a0, a4
 ; RV32IZFINXZDINX-NEXT:    ret
 ;
 ; RV64IZFINXZDINX-LABEL: fcmp_ogt:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    csrr a3, fflags
+; RV64IZFINXZDINX-NEXT:    frflags a3
 ; RV64IZFINXZDINX-NEXT:    flt.d a2, a1, a0
-; RV64IZFINXZDINX-NEXT:    csrw fflags, a3
+; RV64IZFINXZDINX-NEXT:    fsflags a3
 ; RV64IZFINXZDINX-NEXT:    feq.d zero, a1, a0
 ; RV64IZFINXZDINX-NEXT:    mv a0, a2
 ; RV64IZFINXZDINX-NEXT:    ret
@@ -119,18 +119,18 @@ define i32 @fcmp_oge(double %a, double %b) nounwind strictfp {
 ;
 ; RV32IZFINXZDINX-LABEL: fcmp_oge:
 ; RV32IZFINXZDINX:       # %bb.0:
-; RV32IZFINXZDINX-NEXT:    csrr a5, fflags
+; RV32IZFINXZDINX-NEXT:    frflags a5
 ; RV32IZFINXZDINX-NEXT:    fle.d a4, a2, a0
-; RV32IZFINXZDINX-NEXT:    csrw fflags, a5
+; RV32IZFINXZDINX-NEXT:    fsflags a5
 ; RV32IZFINXZDINX-NEXT:    feq.d zero, a2, a0
 ; RV32IZFINXZDINX-NEXT:    mv a0, a4
 ; RV32IZFINXZDINX-NEXT:    ret
 ;
 ; RV64IZFINXZDINX-LABEL: fcmp_oge:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    csrr a3, fflags
+; RV64IZFINXZDINX-NEXT:    frflags a3
 ; RV64IZFINXZDINX-NEXT:    fle.d a2, a1, a0
-; RV64IZFINXZDINX-NEXT:    csrw fflags, a3
+; RV64IZFINXZDINX-NEXT:    fsflags a3
 ; RV64IZFINXZDINX-NEXT:    feq.d zero, a1, a0
 ; RV64IZFINXZDINX-NEXT:    mv a0, a2
 ; RV64IZFINXZDINX-NEXT:    ret
@@ -172,18 +172,18 @@ define i32 @fcmp_olt(double %a, double %b) nounwind strictfp {
 ;
 ; RV32IZFINXZDINX-LABEL: fcmp_olt:
 ; RV32IZFINXZDINX:       # %bb.0:
-; RV32IZFINXZDINX-NEXT:    csrr a5, fflags
+; RV32IZFINXZDINX-NEXT:    frflags a5
 ; RV32IZFINXZDINX-NEXT:    flt.d a4, a0, a2
-; RV32IZFINXZDINX-NEXT:    csrw fflags, a5
+; RV32IZFINXZDINX-NEXT:    fsflags a5
 ; RV32IZFINXZDINX-NEXT:    feq.d zero, a0, a2
 ; RV32IZFINXZDINX-NEXT:    mv a0, a4
 ; RV32IZFINXZDINX-NEXT:    ret
 ;
 ; RV64IZFINXZDINX-LABEL: fcmp_olt:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    csrr a3, fflags
+; RV64IZFINXZDINX-NEXT:    frflags a3
 ; RV64IZFINXZDINX-NEXT:    flt.d a2, a0, a1
-; RV64IZFINXZDINX-NEXT:    csrw fflags, a3
+; RV64IZFINXZDINX-NEXT:    fsflags a3
 ; RV64IZFINXZDINX-NEXT:    feq.d zero, a0, a1
 ; RV64IZFINXZDINX-NEXT:    mv a0, a2
 ; RV64IZFINXZDINX-NEXT:    ret
@@ -223,18 +223,18 @@ define i32 @fcmp_ole(double %a, double %b) nounwind strictfp {
 ;
 ; RV32IZFINXZDINX-LABEL: fcmp_ole:
 ; RV32IZFINXZDINX:       # %bb.0:
-; RV32IZFINXZDINX-NEXT:    csrr a5, fflags
+; RV32IZFINXZDINX-NEXT:    frflags a5
 ; RV32IZFINXZDINX-NEXT:    fle.d a4, a0, a2
-; RV32IZFINXZDINX-NEXT:    csrw fflags, a5
+; RV32IZFINXZDINX-NEXT:    fsflags a5
 ; RV32IZFINXZDINX-NEXT:    feq.d zero, a0, a2
 ; RV32IZFINXZDINX-NEXT:    mv a0, a4
 ; RV32IZFINXZDINX-NEXT:    ret
 ;
 ; RV64IZFINXZDINX-LABEL: fcmp_ole:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    csrr a3, fflags
+; RV64IZFINXZDINX-NEXT:    frflags a3
 ; RV64IZFINXZDINX-NEXT:    fle.d a2, a0, a1
-; RV64IZFINXZDINX-NEXT:    csrw fflags, a3
+; RV64IZFINXZDINX-NEXT:    fsflags a3
 ; RV64IZFINXZDINX-NEXT:    feq.d zero, a0, a1
 ; RV64IZFINXZDINX-NEXT:    mv a0, a2
 ; RV64IZFINXZDINX-NEXT:    ret
@@ -281,13 +281,13 @@ define i32 @fcmp_one(double %a, double %b) nounwind strictfp {
 ;
 ; RV32IZFINXZDINX-LABEL: fcmp_one:
 ; RV32IZFINXZDINX:       # %bb.0:
-; RV32IZFINXZDINX-NEXT:    csrr a4, fflags
+; RV32IZFINXZDINX-NEXT:    frflags a4
 ; RV32IZFINXZDINX-NEXT:    flt.d a5, a0, a2
-; RV32IZFINXZDINX-NEXT:    csrw fflags, a4
+; RV32IZFINXZDINX-NEXT:    fsflags a4
 ; RV32IZFINXZDINX-NEXT:    feq.d zero, a0, a2
-; RV32IZFINXZDINX-NEXT:    csrr a4, fflags
+; RV32IZFINXZDINX-NEXT:    frflags a4
 ; RV32IZFINXZDINX-NEXT:    flt.d a6, a2, a0
-; RV32IZFINXZDINX-NEXT:    csrw fflags, a4
+; RV32IZFINXZDINX-NEXT:    fsflags a4
 ; RV32IZFINXZDINX-NEXT:    or a4, a6, a5
 ; RV32IZFINXZDINX-NEXT:    feq.d zero, a2, a0
 ; RV32IZFINXZDINX-NEXT:    mv a0, a4
@@ -295,13 +295,13 @@ define i32 @fcmp_one(double %a, double %b) nounwind strictfp {
 ;
 ; RV64IZFINXZDINX-LABEL: fcmp_one:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    csrr a2, fflags
+; RV64IZFINXZDINX-NEXT:    frflags a2
 ; RV64IZFINXZDINX-NEXT:    flt.d a3, a0, a1
-; RV64IZFINXZDINX-NEXT:    csrw fflags, a2
+; RV64IZFINXZDINX-NEXT:    fsflags a2
 ; RV64IZFINXZDINX-NEXT:    feq.d zero, a0, a1
-; RV64IZFINXZDINX-NEXT:    csrr a2, fflags
+; RV64IZFINXZDINX-NEXT:    frflags a2
 ; RV64IZFINXZDINX-NEXT:    flt.d a4, a1, a0
-; RV64IZFINXZDINX-NEXT:    csrw fflags, a2
+; RV64IZFINXZDINX-NEXT:    fsflags a2
 ; RV64IZFINXZDINX-NEXT:    or a2, a4, a3
 ; RV64IZFINXZDINX-NEXT:    feq.d zero, a1, a0
 ; RV64IZFINXZDINX-NEXT:    mv a0, a2
@@ -430,13 +430,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
 ;
 ; RV32IZFINXZDINX-LABEL: fcmp_ueq:
 ; RV32IZFINXZDINX:       # %bb.0:
-; RV32IZFINXZDINX-NEXT:    csrr a4, fflags
+; RV32IZFINXZDINX-NEXT:    frflags a4
 ; RV32IZFINXZDINX-NEXT:    flt.d a5, a0, a2
-; RV32IZFINXZDINX-NEXT:    csrw fflags, a4
+; RV32IZFINXZDINX-NEXT:    fsflags a4
 ; RV32IZFINXZDINX-NEXT:    feq.d zero, a0, a2
-; RV32IZFINXZDINX-NEXT:    csrr a4, fflags
+; RV32IZFINXZDINX-NEXT:    frflags a4
 ; RV32IZFINXZDINX-NEXT:    flt.d a6, a2, a0
-; RV32IZFINXZDINX-NEXT:    csrw fflags, a4
+; RV32IZFINXZDINX-NEXT:    fsflags a4
 ; RV32IZFINXZDINX-NEXT:    or a4, a6, a5
 ; RV32IZFINXZDINX-NEXT:    xori a4, a4, 1
 ; RV32IZFINXZDINX-NEXT:    feq.d zero, a2, a0
@@ -445,13 +445,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
 ;
 ; RV64IZFINXZDINX-LABEL: fcmp_ueq:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    csrr a2, fflags
+; RV64IZFINXZDINX-NEXT:    frflags a2
 ; RV64IZFINXZDINX-NEXT:    flt.d a3, a0, a1
-; RV64IZFINXZDINX-NEXT:    csrw fflags, a2
+; RV64IZFINXZDINX-NEXT:    fsflags a2
 ; RV64IZFINXZDINX-NEXT:    feq.d zero, a0, a1
-; RV64IZFINXZDINX-NEXT:    csrr a2, fflags
+; RV64IZFINXZDINX-NEXT:    frflags a2
 ; RV64IZFINXZDINX-NEXT:    flt.d a4, a1, a0
-; RV64IZFINXZDINX-NEXT:    csrw fflags, a2
+; RV64IZFINXZDINX-NEXT:    fsflags a2
 ; RV64IZFINXZDINX-NEXT:    or a3, a4, a3
 ; RV64IZFINXZDINX-NEXT:    xori a2, a3, 1
 ; RV64IZFINXZDINX-NEXT:    feq.d zero, a1, a0
@@ -528,9 +528,9 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp {
 ;
 ; RV32IZFINXZDINX-LABEL: fcmp_ugt:
 ; RV32IZFINXZDINX:       # %bb.0:
-; RV32IZFINXZDINX-NEXT:    csrr a4, fflags
+; RV32IZFINXZDINX-NEXT:    frflags a4
 ; RV32IZFINXZDINX-NEXT:    fle.d a5, a0, a2
-; RV32IZFINXZDINX-NEXT:    csrw fflags, a4
+; RV32IZFINXZDINX-NEXT:    fsflags a4
 ; RV32IZFINXZDINX-NEXT:    xori a4, a5, 1
 ; RV32IZFINXZDINX-NEXT:    feq.d zero, a0, a2
 ; RV32IZFINXZDINX-NEXT:    mv a0, a4
@@ -538,9 +538,9 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp {
 ;
 ; RV64IZFINXZDINX-LABEL: fcmp_ugt:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    csrr a2, fflags
+; RV64IZFINXZDINX-NEXT:    frflags a2
 ; RV64IZFINXZDINX-NEXT:    fle.d a3, a0, a1
-; RV64IZFINXZDINX-NEXT:    csrw fflags, a2
+; RV64IZFINXZDINX-NEXT:    fsflags a2
 ; RV64IZFINXZDINX-NEXT:    xori a2, a3, 1
 ; RV64IZFINXZDINX-NEXT:    feq.d zero, a0, a1
 ; RV64IZFINXZDINX-NEXT:    mv a0, a2
@@ -582,9 +582,9 @@ define i32 @fcmp_uge(double %a, double %b) nounwind strictfp {
 ;
 ; RV32IZFINXZDINX-LABEL: fcmp_uge:
 ; RV32IZFINXZDINX:       # %bb.0:
-; RV32IZFINXZDINX-NEXT:    csrr a4, fflags
+; RV32IZFINXZDINX-NEXT:    frflags a4
 ; RV32IZFINXZDINX-NEXT:    flt.d a5, a0, a2
-; RV32IZFINXZDINX-NEXT:    csrw fflags, a4
+; RV32IZFINXZDINX-NEXT:    fsflags a4
 ; RV32IZFINXZDINX-NEXT:    xori a4, a5, 1
 ; RV32IZFINXZDINX-NEXT:    feq.d zero, a0, a2
 ; RV32IZFINXZDINX-NEXT:    mv a0, a4
@@ -592,9 +592,9 @@ define i32 @fcmp_uge(double %a, double %b) nounwind strictfp {
 ;
 ; RV64IZFINXZDINX-LABEL: fcmp_uge:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    csrr a2, fflags
+; RV64IZFINXZDINX-NEXT:    frflags a2
 ; RV64IZFINXZDINX-NEXT:    flt.d a3, a0, a1
-; RV64IZFINXZDINX-NEXT:    csrw fflags, a2
+; RV64IZFINXZDINX-NEXT:    fsflags a2
 ; RV64IZFINXZDINX-NEXT:    xori a2, a3, 1
 ; RV64IZFINXZDINX-NEXT:    feq.d zero, a0, a1
 ; RV64IZFINXZDINX-NEXT:    mv a0, a2
@@ -638,9 +638,9 @@ define i32 @fcmp_ult(double %a, double %b) nounwind strictfp {
 ;
 ; RV32IZFINXZDINX-LABEL: fcmp_ult:
 ; RV32IZFINXZDINX:       # %bb.0:
-; RV32IZFINXZDINX-NEXT:    csrr a4, fflags
+; RV32IZFINXZDINX-NEXT:    frflags a4
 ; RV32IZFINXZDINX-NEXT:    fle.d a5, a2, a0
-; RV32IZFINXZDINX-NEXT:    csrw fflags, a4
+; RV32IZFINXZDINX-NEXT:    fsflags a4
 ; RV32IZFINXZDINX-NEXT:    xori a4, a5, 1
 ; RV32IZFINXZDINX-NEXT:    feq.d zero, a2, a0
 ; RV32IZFINXZDINX-NEXT:    mv a0, a4
@@ -648,9 +648,9 @@ define i32 @fcmp_ult(double %a, double %b) nounwind strictfp {
 ;
 ; RV64IZFINXZDINX-LABEL: fcmp_ult:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    csrr a2, fflags
+; RV64IZFINXZDINX-NEXT:    frflags a2
 ; RV64IZFINXZDINX-NEXT:    fle.d a3, a1, a0
-; RV64IZFINXZDINX-NEXT:    csrw fflags, a2
+; RV64IZFINXZDINX-NEXT:    fsflags a2
 ; RV64IZFINXZDINX-NEXT:    xori a2, a3, 1
 ; RV64IZFINXZDINX-NEXT:    feq.d zero, a1, a0
 ; RV64IZFINXZDINX-NEXT:    mv a0, a2
@@ -692,9 +692,9 @@ define i32 @fcmp_ule(double %a, double %b) nounwind strictfp {
 ;
 ; RV32IZFINXZDINX-LABEL: fcmp_ule:
 ; RV32IZFINXZDINX:       # %bb.0:
-; RV32IZFINXZDINX-NEXT:    csrr a4, fflags
+; RV32IZFINXZDINX-NEXT:    frflags a4
 ; RV32IZFINXZDINX-NEXT:    flt.d a5, a2, a0
-; RV32IZFINXZDINX-NEXT:    csrw fflags, a4
+; RV32IZFINXZDINX-NEXT:    fsflags a4
 ; RV32IZFINXZDINX-NEXT:    xori a4, a5, 1
 ; RV32IZFINXZDINX-NEXT:    feq.d zero, a2, a0
 ; RV32IZFINXZDINX-NEXT:    mv a0, a4
@@ -702,9 +702,9 @@ define i32 @fcmp_ule(double %a, double %b) nounwind strictfp {
 ;
 ; RV64IZFINXZDINX-LABEL: fcmp_ule:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    csrr a2, fflags
+; RV64IZFINXZDINX-NEXT:    frflags a2
 ; RV64IZFINXZDINX-NEXT:    flt.d a3, a1, a0
-; RV64IZFINXZDINX-NEXT:    csrw fflags, a2
+; RV64IZFINXZDINX-NEXT:    fsflags a2
 ; RV64IZFINXZDINX-NEXT:    xori a2, a3, 1
 ; RV64IZFINXZDINX-NEXT:    feq.d zero, a1, a0
 ; RV64IZFINXZDINX-NEXT:    mv a0, a2
diff --git a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
index dae9f3e089cf4a..0cbfc96bf485ef 100644
--- a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
+++ b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
@@ -63,9 +63,9 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind strictfp {
 ;
 ; CHECKIZFINX-LABEL: fcmp_ogt:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    csrr a3, fflags
+; CHECKIZFINX-NEXT:    frflags a3
 ; CHECKIZFINX-NEXT:    flt.s a2, a1, a0
-; CHECKIZFINX-NEXT:    csrw fflags, a3
+; CHECKIZFINX-NEXT:    fsflags a3
 ; CHECKIZFINX-NEXT:    feq.s zero, a1, a0
 ; CHECKIZFINX-NEXT:    mv a0, a2
 ; CHECKIZFINX-NEXT:    ret
@@ -105,9 +105,9 @@ define i32 @fcmp_oge(float %a, float %b) nounwind strictfp {
 ;
 ; CHECKIZFINX-LABEL: fcmp_oge:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    csrr a3, fflags
+; CHECKIZFINX-NEXT:    frflags a3
 ; CHECKIZFINX-NEXT:    fle.s a2, a1, a0
-; CHECKIZFINX-NEXT:    csrw fflags, a3
+; CHECKIZFINX-NEXT:    fsflags a3
 ; CHECKIZFINX-NEXT:    feq.s zero, a1, a0
 ; CHECKIZFINX-NEXT:    mv a0, a2
 ; CHECKIZFINX-NEXT:    ret
@@ -149,9 +149,9 @@ define i32 @fcmp_olt(float %a, float %b) nounwind strictfp {
 ;
 ; CHECKIZFINX-LABEL: fcmp_olt:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    csrr a3, fflags
+; CHECKIZFINX-NEXT:    frflags a3
 ; CHECKIZFINX-NEXT:    flt.s a2, a0, a1
-; CHECKIZFINX-NEXT:    csrw fflags, a3
+; CHECKIZFINX-NEXT:    fsflags a3
 ; CHECKIZFINX-NEXT:    feq.s zero, a0, a1
 ; CHECKIZFINX-NEXT:    mv a0, a2
 ; CHECKIZFINX-NEXT:    ret
@@ -191,9 +191,9 @@ define i32 @fcmp_ole(float %a, float %b) nounwind strictfp {
 ;
 ; CHECKIZFINX-LABEL: fcmp_ole:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    csrr a3, fflags
+; CHECKIZFINX-NEXT:    frflags a3
 ; CHECKIZFINX-NEXT:    fle.s a2, a0, a1
-; CHECKIZFINX-NEXT:    csrw fflags, a3
+; CHECKIZFINX-NEXT:    fsflags a3
 ; CHECKIZFINX-NEXT:    feq.s zero, a0, a1
 ; CHECKIZFINX-NEXT:    mv a0, a2
 ; CHECKIZFINX-NEXT:    ret
@@ -240,13 +240,13 @@ define i32 @fcmp_one(float %a, float %b) nounwind strictfp {
 ;
 ; CHECKIZFINX-LABEL: fcmp_one:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    csrr a2, fflags
+; CHECKIZFINX-NEXT:    frflags a2
 ; CHECKIZFINX-NEXT:    flt.s a3, a0, a1
-; CHECKIZFINX-NEXT:    csrw fflags, a2
+; CHECKIZFINX-NEXT:    fsflags a2
 ; CHECKIZFINX-NEXT:    feq.s zero, a0, a1
-; CHECKIZFINX-NEXT:    csrr a2, fflags
+; CHECKIZFINX-NEXT:    frflags a2
 ; CHECKIZFINX-NEXT:    flt.s a4, a1, a0
-; CHECKIZFINX-NEXT:    csrw fflags, a2
+; CHECKIZFINX-NEXT:    fsflags a2
 ; CHECKIZFINX-NEXT:    or a2, a4, a3
 ; CHECKIZFINX-NEXT:    feq.s zero, a1, a0
 ; CHECKIZFINX-NEXT:    mv a0, a2
@@ -360,13 +360,13 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind strictfp {
 ;
 ; CHECKIZFINX-LABEL: fcmp_ueq:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    csrr a2, fflags
+; CHECKIZFINX-NEXT:    frflags a2
 ; CHECKIZFINX-NEXT:    flt.s a3, a0, a1
-; CHECKIZFINX-NEXT:    csrw fflags, a2
+; CHECKIZFINX-NEXT:    fsflags a2
 ; CHECKIZFINX-NEXT:    feq.s zero, a0, a1
-; CHECKIZFINX-NEXT:    csrr a2, fflags
+; CHECKIZFINX-NEXT:    frflags a2
 ; CHECKIZFINX-NEXT:    flt.s a4, a1, a0
-; CHECKIZFINX-NEXT:    csrw fflags, a2
+; CHECKIZFINX-NEXT:    fsflags a2
 ; CHECKIZFINX-NEXT:    or a3, a4, a3
 ; CHECKIZFINX-NEXT:    xori a2, a3, 1
 ; CHECKIZFINX-NEXT:    feq.s zero, a1, a0
@@ -435,9 +435,9 @@ define i32 @fcmp_ugt(float %a, float %b) nounwind strictfp {
 ;
 ; CHECKIZFINX-LABEL: fcmp_ugt:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    csrr a2, fflags
+; CHECKIZFINX-NEXT:    frflags a2
 ; CHECKIZFINX-NEXT:    fle.s a3, a0, a1
-; CHECKIZFINX-NEXT:    csrw fflags, a2
+; CHECKIZFINX-NEXT:    fsflags a2
 ; CHECKIZFINX-NEXT:    xori a2, a3, 1
 ; CHECKIZFINX-NEXT:    feq.s zero, a0, a1
 ; CHECKIZFINX-NEXT:    mv a0, a2
@@ -479,9 +479,9 @@ define i32 @fcmp_uge(float %a, float %b) nounwind strictfp {
 ;
 ; CHECKIZFINX-LABEL: fcmp_uge:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    csrr a2, fflags
+; CHECKIZFINX-NEXT:    frflags a2
 ; CHECKIZFINX-NEXT:    flt.s a3, a0, a1
-; CHECKIZFINX-NEXT:    csrw fflags, a2
+; CHECKIZFINX-NEXT:    fsflags a2
 ; CHECKIZFINX-NEXT:    xori a2, a3, 1
 ; CHECKIZFINX-NEXT:    feq.s zero, a0, a1
 ; CHECKIZFINX-NEXT:    mv a0, a2
@@ -525,9 +525,9 @@ define i32 @fcmp_ult(float %a, float %b) nounwind strictfp {
 ;
 ; CHECKIZFINX-LABEL: fcmp_ult:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    csrr a2, fflags
+; CHECKIZFINX-NEXT:    frflags a2
 ; CHECKIZFINX-NEXT:    fle.s a3, a1, a0
-; CHECKIZFINX-NEXT:    csrw fflags, a2
+; CHECKIZFINX-NEXT:    fsflags a2
 ; CHECKIZFINX-NEXT:    xori a2, a3, 1
 ; CHECKIZFINX-NEXT:    feq.s zero, a1, a0
 ; CHECKIZFINX-NEXT:    mv a0, a2
@@ -569,9 +569,9 @@ define i32 @fcmp_ule(float %a, float %b) nounwind strictfp {
 ;
 ; CHECKIZFINX-LABEL: fcmp_ule:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    csrr a2, fflags
+; CHECKIZFINX-NEXT:    frflags a2
 ; CHECKIZFINX-NEXT:    flt.s a3, a1, a0
-; CHECKIZFINX-NEXT:    csrw fflags, a2
+; CHECKIZFINX-NEXT:    fsflags a2
 ; CHECKIZFINX-NEXT:    xori a2, a3, 1
 ; CHECKIZFINX-NEXT:    feq.s zero, a1, a0
 ; CHECKIZFINX-NEXT:    mv a0, a2
diff --git a/llvm/test/CodeGen/RISCV/half-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
index d96c39c504e1fd..4bc595bcc4cc8f 100644
--- a/llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
@@ -61,9 +61,9 @@ define i32 @fcmp_ogt(half %a, half %b) nounwind strictfp {
 ;
 ; CHECKIZHINX-LABEL: fcmp_ogt:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    csrr a3, fflags
+; CHECKIZHINX-NEXT:    frflags a3
 ; CHECKIZHINX-NEXT:    flt.h a2, a1, a0
-; CHECKIZHINX-NEXT:    csrw fflags, a3
+; CHECKIZHINX-NEXT:    fsflags a3
 ; CHECKIZHINX-NEXT:    feq.h zero, a1, a0
 ; CHECKIZHINX-NEXT:    mv a0, a2
 ; CHECKIZHINX-NEXT...
[truncated]

dtcxzyw
dtcxzyw approved these changes Sep 13, 2024
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LGTM. These pseudoinstructions are recognized by GNU as with zfinx.

@topperc topperc merged commit 7ba4968 into llvm:main Sep 13, 2024
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@topperc topperc deleted the pr/csr-aliases branch September 25, 2024 04:45
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@dtcxzyw dtcxzyw dtcxzyw approved these changes

@asb asb Awaiting requested review from asb

@realqhc realqhc Awaiting requested review from realqhc

@wangpc-pp wangpc-pp Awaiting requested review from wangpc-pp

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@topperc @llvmbot @dtcxzyw