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[RISCV] Enable floating point CSR alias mnemonics for Zfinx. #108464

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Merged
merged 2 commits into from
Sep 13, 2024
Merged

[RISCV] Enable floating point CSR alias mnemonics for Zfinx. #108464

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4b49313
[RISCV] Enable floating point CSR alias mnemonics for Zfinx.
topperc Sep 12, 2024
d36ad23
fixup! update comment
topperc Sep 12, 2024
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5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Original file line number Diff line number Diff line change
Expand Up @@ -348,6 +348,11 @@ def FeatureStdExtZfinx
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
def HasStdExtFOrZfinx : Predicate<"Subtarget->hasStdExtFOrZfinx()">,
AssemblerPredicate<(any_of FeatureStdExtF,
FeatureStdExtZfinx),
"'F' (Single-Precision Floating-Point) or "
"'Zfinx' (Float in Integer)">;

def FeatureStdExtZdinx
: RISCVExtension<"zdinx", 1, 0,
Expand Down
35 changes: 19 additions & 16 deletions llvm/lib/Target/RISCV/RISCVInstrInfoF.td
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Original file line number Diff line number Diff line change
Expand Up @@ -400,23 +400,10 @@ def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
//===----------------------------------------------------------------------===//

let Predicates = [HasStdExtF] in {
def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>;
def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;

def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;

// fgt.s/fge.s are recognised by the GNU assembler but the canonical
// flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
def : InstAlias<"fgt.s $rd, $rs, $rt",
(FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
def : InstAlias<"fge.s $rd, $rs, $rt",
(FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;

let Predicates = [HasStdExtFOrZfinx] in {
// The following csr instructions actually alias instructions from the base ISA.
// However, it only makes sense to support them when the F extension is enabled.
// However, it only makes sense to support them when the F or Zfinx extension is
// enabled.
// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr".
def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 2>;
def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs)>;
Expand All @@ -439,6 +426,22 @@ def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, SysRegFFLAGS.Encoding, GP
def : InstAlias<"fsflags $rs", (CSRRW X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>;
def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>;
def : InstAlias<"fsflagsi $imm", (CSRRWI X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>;
} // Predicates = [HasStdExtFOrZfinx]

let Predicates = [HasStdExtF] in {
def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>;
def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;

def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;

// fgt.s/fge.s are recognised by the GNU assembler but the canonical
// flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
def : InstAlias<"fgt.s $rd, $rs, $rt",
(FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
def : InstAlias<"fge.s $rd, $rs, $rt",
(FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;

// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both
// spellings should be supported by standard tools.
Expand Down
96 changes: 48 additions & 48 deletions llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -68,18 +68,18 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ogt:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: csrr a5, fflags
; RV32IZFINXZDINX-NEXT: frflags a5
; RV32IZFINXZDINX-NEXT: flt.d a4, a2, a0
; RV32IZFINXZDINX-NEXT: csrw fflags, a5
; RV32IZFINXZDINX-NEXT: fsflags a5
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ogt:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: csrr a3, fflags
; RV64IZFINXZDINX-NEXT: frflags a3
; RV64IZFINXZDINX-NEXT: flt.d a2, a1, a0
; RV64IZFINXZDINX-NEXT: csrw fflags, a3
; RV64IZFINXZDINX-NEXT: fsflags a3
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
; RV64IZFINXZDINX-NEXT: mv a0, a2
; RV64IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -119,18 +119,18 @@ define i32 @fcmp_oge(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_oge:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: csrr a5, fflags
; RV32IZFINXZDINX-NEXT: frflags a5
; RV32IZFINXZDINX-NEXT: fle.d a4, a2, a0
; RV32IZFINXZDINX-NEXT: csrw fflags, a5
; RV32IZFINXZDINX-NEXT: fsflags a5
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_oge:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: csrr a3, fflags
; RV64IZFINXZDINX-NEXT: frflags a3
; RV64IZFINXZDINX-NEXT: fle.d a2, a1, a0
; RV64IZFINXZDINX-NEXT: csrw fflags, a3
; RV64IZFINXZDINX-NEXT: fsflags a3
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
; RV64IZFINXZDINX-NEXT: mv a0, a2
; RV64IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -172,18 +172,18 @@ define i32 @fcmp_olt(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_olt:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: csrr a5, fflags
; RV32IZFINXZDINX-NEXT: frflags a5
; RV32IZFINXZDINX-NEXT: flt.d a4, a0, a2
; RV32IZFINXZDINX-NEXT: csrw fflags, a5
; RV32IZFINXZDINX-NEXT: fsflags a5
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_olt:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: csrr a3, fflags
; RV64IZFINXZDINX-NEXT: frflags a3
; RV64IZFINXZDINX-NEXT: flt.d a2, a0, a1
; RV64IZFINXZDINX-NEXT: csrw fflags, a3
; RV64IZFINXZDINX-NEXT: fsflags a3
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
; RV64IZFINXZDINX-NEXT: mv a0, a2
; RV64IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -223,18 +223,18 @@ define i32 @fcmp_ole(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ole:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: csrr a5, fflags
; RV32IZFINXZDINX-NEXT: frflags a5
; RV32IZFINXZDINX-NEXT: fle.d a4, a0, a2
; RV32IZFINXZDINX-NEXT: csrw fflags, a5
; RV32IZFINXZDINX-NEXT: fsflags a5
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ole:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: csrr a3, fflags
; RV64IZFINXZDINX-NEXT: frflags a3
; RV64IZFINXZDINX-NEXT: fle.d a2, a0, a1
; RV64IZFINXZDINX-NEXT: csrw fflags, a3
; RV64IZFINXZDINX-NEXT: fsflags a3
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
; RV64IZFINXZDINX-NEXT: mv a0, a2
; RV64IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -281,27 +281,27 @@ define i32 @fcmp_one(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_one:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: flt.d a5, a0, a2
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: flt.d a6, a2, a0
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: or a4, a6, a5
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_one:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: flt.d a3, a0, a1
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: flt.d a4, a1, a0
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: or a2, a4, a3
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
; RV64IZFINXZDINX-NEXT: mv a0, a2
Expand Down Expand Up @@ -430,13 +430,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ueq:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: flt.d a5, a0, a2
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: flt.d a6, a2, a0
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: or a4, a6, a5
; RV32IZFINXZDINX-NEXT: xori a4, a4, 1
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
Expand All @@ -445,13 +445,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
;
; RV64IZFINXZDINX-LABEL: fcmp_ueq:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: flt.d a3, a0, a1
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: flt.d a4, a1, a0
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: or a3, a4, a3
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
Expand Down Expand Up @@ -528,19 +528,19 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ugt:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: fle.d a5, a0, a2
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ugt:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: fle.d a3, a0, a1
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
; RV64IZFINXZDINX-NEXT: mv a0, a2
Expand Down Expand Up @@ -582,19 +582,19 @@ define i32 @fcmp_uge(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_uge:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: flt.d a5, a0, a2
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_uge:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: flt.d a3, a0, a1
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
; RV64IZFINXZDINX-NEXT: mv a0, a2
Expand Down Expand Up @@ -638,19 +638,19 @@ define i32 @fcmp_ult(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ult:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: fle.d a5, a2, a0
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ult:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: fle.d a3, a1, a0
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
; RV64IZFINXZDINX-NEXT: mv a0, a2
Expand Down Expand Up @@ -692,19 +692,19 @@ define i32 @fcmp_ule(double %a, double %b) nounwind strictfp {
;
; RV32IZFINXZDINX-LABEL: fcmp_ule:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
; RV32IZFINXZDINX-NEXT: frflags a4
; RV32IZFINXZDINX-NEXT: flt.d a5, a2, a0
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
; RV32IZFINXZDINX-NEXT: fsflags a4
; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
; RV32IZFINXZDINX-NEXT: mv a0, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fcmp_ule:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
; RV64IZFINXZDINX-NEXT: frflags a2
; RV64IZFINXZDINX-NEXT: flt.d a3, a1, a0
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
; RV64IZFINXZDINX-NEXT: fsflags a2
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
; RV64IZFINXZDINX-NEXT: mv a0, a2
Expand Down
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