[X86] Add missing immediate qualifier to the (V)INSERT/EXTRACT/PERM2 instruction names #108593
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
@llvm/pr-subscribers-llvm-globalisel Author: Simon Pilgrim (RKSimon) ChangesMakes it easier to algorithmically recreate the instruction name in various analysis scripts I'm working on Patch is 71.31 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/108593.diff 31 Files Affected:
diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
index 2fb499122fbbfb..d2ee0f1bac6831 100644
--- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
@@ -1255,16 +1255,16 @@ bool X86InstructionSelector::selectExtract(MachineInstr &I,
if (SrcTy.getSizeInBits() == 256 && DstTy.getSizeInBits() == 128) {
if (HasVLX)
- I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr));
+ I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rri));
else if (HasAVX)
- I.setDesc(TII.get(X86::VEXTRACTF128rr));
+ I.setDesc(TII.get(X86::VEXTRACTF128rri));
else
return false;
} else if (SrcTy.getSizeInBits() == 512 && HasAVX512) {
if (DstTy.getSizeInBits() == 128)
- I.setDesc(TII.get(X86::VEXTRACTF32x4Zrr));
+ I.setDesc(TII.get(X86::VEXTRACTF32x4Zrri));
else if (DstTy.getSizeInBits() == 256)
- I.setDesc(TII.get(X86::VEXTRACTF64x4Zrr));
+ I.setDesc(TII.get(X86::VEXTRACTF64x4Zrri));
else
return false;
} else
@@ -1388,16 +1388,16 @@ bool X86InstructionSelector::selectInsert(MachineInstr &I,
if (DstTy.getSizeInBits() == 256 && InsertRegTy.getSizeInBits() == 128) {
if (HasVLX)
- I.setDesc(TII.get(X86::VINSERTF32x4Z256rr));
+ I.setDesc(TII.get(X86::VINSERTF32x4Z256rri));
else if (HasAVX)
- I.setDesc(TII.get(X86::VINSERTF128rr));
+ I.setDesc(TII.get(X86::VINSERTF128rri));
else
return false;
} else if (DstTy.getSizeInBits() == 512 && HasAVX512) {
if (InsertRegTy.getSizeInBits() == 128)
- I.setDesc(TII.get(X86::VINSERTF32x4Zrr));
+ I.setDesc(TII.get(X86::VINSERTF32x4Zrri));
else if (InsertRegTy.getSizeInBits() == 256)
- I.setDesc(TII.get(X86::VINSERTF64x4Zrr));
+ I.setDesc(TII.get(X86::VINSERTF64x4Zrri));
else
return false;
} else
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
index 9cc72d32d85f94..ca6b82cd0f1e6f 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
@@ -1158,13 +1158,13 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
DestName = getRegName(MI->getOperand(0).getReg());
break;
- case X86::VPERM2F128rr:
- case X86::VPERM2I128rr:
+ case X86::VPERM2F128rri:
+ case X86::VPERM2I128rri:
Src2Name = getRegName(MI->getOperand(2).getReg());
[[fallthrough]];
- case X86::VPERM2F128rm:
- case X86::VPERM2I128rm:
+ case X86::VPERM2F128rmi:
+ case X86::VPERM2I128rmi:
// For instruction comments purpose, assume the 256-bit vector is v4i64.
if (MI->getOperand(NumOperands - 1).isImm())
DecodeVPERM2X128Mask(4, MI->getOperand(NumOperands - 1).getImm(),
diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp
index 7343af1bdc9a5a..a909440f983173 100644
--- a/llvm/lib/Target/X86/X86CompressEVEX.cpp
+++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp
@@ -138,8 +138,8 @@ static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) {
case X86::VSHUFI32X4Z256rri:
case X86::VSHUFI64X2Z256rmi:
case X86::VSHUFI64X2Z256rri: {
- assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
- NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
+ assert((NewOpc == X86::VPERM2F128rri || NewOpc == X86::VPERM2I128rri ||
+ NewOpc == X86::VPERM2F128rmi || NewOpc == X86::VPERM2I128rmi) &&
"Unexpected new opcode!");
MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
int64_t ImmVal = Imm.getImm();
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index c9885242131238..a9ee128bf54cfc 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -368,7 +368,7 @@ multiclass vinsert_for_size_split<int Opcode, X86VectorVTInfo From,
SDPatternOperator vinsert_for_mask,
X86FoldableSchedWrite sched> {
let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
- defm rr : AVX512_maskable_split<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
+ defm rri : AVX512_maskable_split<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
(ins To.RC:$src1, From.RC:$src2, u8imm:$src3),
"vinsert" # From.EltTypeName # "x" # From.NumElts,
"$src3, $src2, $src1", "$src1, $src2, $src3",
@@ -380,7 +380,7 @@ multiclass vinsert_for_size_split<int Opcode, X86VectorVTInfo From,
(iPTR imm))>,
AVX512AIi8Base, EVEX, VVVV, Sched<[sched]>;
let mayLoad = 1 in
- defm rm : AVX512_maskable_split<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
+ defm rmi : AVX512_maskable_split<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
(ins To.RC:$src1, From.MemOp:$src2, u8imm:$src3),
"vinsert" # From.EltTypeName # "x" # From.NumElts,
"$src3, $src2, $src1", "$src1, $src2, $src3",
@@ -408,7 +408,7 @@ multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
let Predicates = p in {
def : Pat<(vinsert_insert:$ins
(To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
- (To.VT (!cast<Instruction>(InstrStr#"rr")
+ (To.VT (!cast<Instruction>(InstrStr#"rri")
To.RC:$src1, From.RC:$src2,
(INSERT_get_vinsert_imm To.RC:$ins)))>;
@@ -416,7 +416,7 @@ multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
(To.VT To.RC:$src1),
(From.VT (From.LdFrag addr:$src2)),
(iPTR imm)),
- (To.VT (!cast<Instruction>(InstrStr#"rm")
+ (To.VT (!cast<Instruction>(InstrStr#"rmi")
To.RC:$src1, addr:$src2,
(INSERT_get_vinsert_imm To.RC:$ins)))>;
}
@@ -529,7 +529,7 @@ let Predicates = p in {
(From.VT From.RC:$src2),
(iPTR imm))),
Cast.RC:$src0)),
- (!cast<Instruction>(InstrStr#"rrk")
+ (!cast<Instruction>(InstrStr#"rrik")
Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
(INSERT_get_vinsert_imm To.RC:$ins))>;
def : Pat<(Cast.VT
@@ -541,7 +541,7 @@ let Predicates = p in {
(From.LdFrag addr:$src2))),
(iPTR imm))),
Cast.RC:$src0)),
- (!cast<Instruction>(InstrStr#"rmk")
+ (!cast<Instruction>(InstrStr#"rmik")
Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, addr:$src2,
(INSERT_get_vinsert_imm To.RC:$ins))>;
@@ -552,7 +552,7 @@ let Predicates = p in {
(From.VT From.RC:$src2),
(iPTR imm))),
Cast.ImmAllZerosV)),
- (!cast<Instruction>(InstrStr#"rrkz")
+ (!cast<Instruction>(InstrStr#"rrikz")
Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
(INSERT_get_vinsert_imm To.RC:$ins))>;
def : Pat<(Cast.VT
@@ -562,7 +562,7 @@ let Predicates = p in {
(From.VT (From.LdFrag addr:$src2)),
(iPTR imm))),
Cast.ImmAllZerosV)),
- (!cast<Instruction>(InstrStr#"rmkz")
+ (!cast<Instruction>(InstrStr#"rmikz")
Cast.KRCWM:$mask, To.RC:$src1, addr:$src2,
(INSERT_get_vinsert_imm To.RC:$ins))>;
}
@@ -677,7 +677,7 @@ multiclass vextract_for_size_split<int Opcode,
SchedWrite SchedRR, SchedWrite SchedMR> {
let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
- defm rr : AVX512_maskable_split<Opcode, MRMDestReg, To, (outs To.RC:$dst),
+ defm rri : AVX512_maskable_split<Opcode, MRMDestReg, To, (outs To.RC:$dst),
(ins From.RC:$src1, u8imm:$idx),
"vextract" # To.EltTypeName # "x" # To.NumElts,
"$idx, $src1", "$src1, $idx",
@@ -685,7 +685,7 @@ multiclass vextract_for_size_split<int Opcode,
(vextract_for_mask:$idx (From.VT From.RC:$src1), (iPTR imm))>,
AVX512AIi8Base, EVEX, Sched<[SchedRR]>;
- def mr : AVX512AIi8<Opcode, MRMDestMem, (outs),
+ def mri : AVX512AIi8<Opcode, MRMDestMem, (outs),
(ins To.MemOp:$dst, From.RC:$src1, u8imm:$idx),
"vextract" # To.EltTypeName # "x" # To.NumElts #
"\t{$idx, $src1, $dst|$dst, $src1, $idx}",
@@ -695,7 +695,7 @@ multiclass vextract_for_size_split<int Opcode,
Sched<[SchedMR]>;
let mayStore = 1, hasSideEffects = 0 in
- def mrk : AVX512AIi8<Opcode, MRMDestMem, (outs),
+ def mrik : AVX512AIi8<Opcode, MRMDestMem, (outs),
(ins To.MemOp:$dst, To.KRCWM:$mask,
From.RC:$src1, u8imm:$idx),
"vextract" # To.EltTypeName # "x" # To.NumElts #
@@ -718,12 +718,12 @@ multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> {
let Predicates = p in {
def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
- (To.VT (!cast<Instruction>(InstrStr#"rr")
+ (To.VT (!cast<Instruction>(InstrStr#"rri")
From.RC:$src1,
(EXTRACT_get_vextract_imm To.RC:$ext)))>;
def : Pat<(store (To.VT (vextract_extract:$ext (From.VT From.RC:$src1),
(iPTR imm))), addr:$dst),
- (!cast<Instruction>(InstrStr#"mr") addr:$dst, From.RC:$src1,
+ (!cast<Instruction>(InstrStr#"mri") addr:$dst, From.RC:$src1,
(EXTRACT_get_vextract_imm To.RC:$ext))>;
}
}
@@ -828,31 +828,31 @@ defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v32bf16_info, v16bf16x_info,
// smaller extract to enable EVEX->VEX.
let Predicates = [NoVLX, HasEVEX512] in {
def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))),
- (v2i64 (VEXTRACTI128rr
+ (v2i64 (VEXTRACTI128rri
(v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))),
- (v2f64 (VEXTRACTF128rr
+ (v2f64 (VEXTRACTF128rri
(v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))),
- (v4i32 (VEXTRACTI128rr
+ (v4i32 (VEXTRACTI128rri
(v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))),
- (v4f32 (VEXTRACTF128rr
+ (v4f32 (VEXTRACTF128rri
(v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))),
- (v8i16 (VEXTRACTI128rr
+ (v8i16 (VEXTRACTI128rri
(v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v8f16 (extract_subvector (v32f16 VR512:$src), (iPTR 8))),
- (v8f16 (VEXTRACTF128rr
+ (v8f16 (VEXTRACTF128rri
(v16f16 (EXTRACT_SUBREG (v32f16 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
- (v16i8 (VEXTRACTI128rr
+ (v16i8 (VEXTRACTI128rri
(v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
(iPTR 1)))>;
}
@@ -861,31 +861,31 @@ def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
// smaller extract to enable EVEX->VEX.
let Predicates = [HasVLX] in {
def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))),
- (v2i64 (VEXTRACTI32x4Z256rr
+ (v2i64 (VEXTRACTI32x4Z256rri
(v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))),
- (v2f64 (VEXTRACTF32x4Z256rr
+ (v2f64 (VEXTRACTF32x4Z256rri
(v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))),
- (v4i32 (VEXTRACTI32x4Z256rr
+ (v4i32 (VEXTRACTI32x4Z256rri
(v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))),
- (v4f32 (VEXTRACTF32x4Z256rr
+ (v4f32 (VEXTRACTF32x4Z256rri
(v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))),
- (v8i16 (VEXTRACTI32x4Z256rr
+ (v8i16 (VEXTRACTI32x4Z256rri
(v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v8f16 (extract_subvector (v32f16 VR512:$src), (iPTR 8))),
- (v8f16 (VEXTRACTF32x4Z256rr
+ (v8f16 (VEXTRACTF32x4Z256rri
(v16f16 (EXTRACT_SUBREG (v32f16 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
- (v16i8 (VEXTRACTI32x4Z256rr
+ (v16i8 (VEXTRACTI32x4Z256rri
(v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
(iPTR 1)))>;
}
@@ -904,7 +904,7 @@ let Predicates = p in {
(To.VT (vextract_extract:$ext
(From.VT From.RC:$src), (iPTR imm)))),
To.RC:$src0)),
- (Cast.VT (!cast<Instruction>(InstrStr#"rrk")
+ (Cast.VT (!cast<Instruction>(InstrStr#"rrik")
Cast.RC:$src0, Cast.KRCWM:$mask, From.RC:$src,
(EXTRACT_get_vextract_imm To.RC:$ext)))>;
@@ -913,7 +913,7 @@ let Predicates = p in {
(To.VT (vextract_extract:$ext
(From.VT From.RC:$src), (iPTR imm)))),
Cast.ImmAllZerosV)),
- (Cast.VT (!cast<Instruction>(InstrStr#"rrkz")
+ (Cast.VT (!cast<Instruction>(InstrStr#"rrikz")
Cast.KRCWM:$mask, From.RC:$src,
(EXTRACT_get_vextract_imm To.RC:$ext)))>;
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 401b8ce71edaf5..0a159db91ff5a2 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -2597,8 +2597,8 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
.setImm(X86::getSwappedVCMPImm(
MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f));
break;
- case X86::VPERM2F128rr:
- case X86::VPERM2I128rr:
+ case X86::VPERM2F128rri:
+ case X86::VPERM2I128rri:
// Flip permute source immediate.
// Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
// Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
@@ -6258,16 +6258,16 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
case X86::VMOVAPSZ128mr_NOVLX:
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
- get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
+ get(X86::VEXTRACTF32x4Zmri), X86::sub_xmm);
case X86::VMOVUPSZ128mr_NOVLX:
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
- get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
+ get(X86::VEXTRACTF32x4Zmri), X86::sub_xmm);
case X86::VMOVAPSZ256mr_NOVLX:
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
- get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
+ get(X86::VEXTRACTF64x4Zmri), X86::sub_ymm);
case X86::VMOVUPSZ256mr_NOVLX:
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
- get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
+ get(X86::VEXTRACTF64x4Zmri), X86::sub_ymm);
case X86::MOV32ri64: {
Register Reg = MIB.getReg(0);
Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
@@ -6775,8 +6775,8 @@ static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
case X86::VPACKUSWBZ128rr:
case X86::VPACKSSDWZ128rr:
case X86::VPACKUSDWZ128rr:
- case X86::VPERM2F128rr:
- case X86::VPERM2I128rr:
+ case X86::VPERM2F128rri:
+ case X86::VPERM2I128rri:
case X86::VSHUFF32X4Z256rri:
case X86::VSHUFF32X4Zrri:
case X86::VSHUFF64X2Z256rri:
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 4e5f2e3f872ad4..278ae9a09d45d6 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -7164,11 +7164,11 @@ let Predicates = [HasAVXNECONVERT, NoVLX] in
let ExeDomain = SSEPackedSingle in {
let isCommutable = 1 in
-def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
+def VPERM2F128rri : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
(ins VR256:$src1, VR256:$src2, u8imm:$src3),
"vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", []>,
VEX, VVVV, VEX_L, Sched<[WriteFShuffle256]>;
-def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
+def VPERM2F128rmi : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
(ins VR256:$src1, f256mem:$src2, u8imm:$src3),
"vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", []>,
VEX, VVVV, VEX_L, Sched<[WriteFShuffle256.Folded, WriteFShuffle256.ReadAfterFold]>;
@@ -7181,12 +7181,12 @@ def Perm2XCommuteImm : SDNodeXForm<timm, [{
multiclass vperm2x128_lowering<string InstrStr, ValueType VT, PatFrag memop_frag> {
def : Pat<(VT (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 timm:$imm))),
- (!cast<Instruction>(InstrStr#rr) VR256:$src1, VR256:$src2, timm:$imm)>;
+ (!cast<Instruction>(InstrStr#rri) VR256:$src1, VR256:$src2, timm:$imm)>;
def : Pat<(VT (X86VPerm2x128 VR256:$src1, (memop_frag addr:$src2), (i8 timm:$imm))),
- (!cast<Instruction>(InstrStr#rm) VR256:$src1, addr:$src2, timm:$imm)>;
+ (!cast<Instruction>(InstrStr#rmi) VR256:$src1, addr:$src2, timm:$imm)>;
// Pattern with load in other operand.
def : Pat<(VT (X86VPerm2x128 (memop_frag addr:$src2), VR256:$src1, (i8 timm:$imm))),
- (!cast<Instruction>(InstrStr#rm) VR256:$src1, addr:$src2,
+ (!cast<Instruction>(InstrStr#rmi) VR256:$src1, addr:$src2,
(Perm2XCommuteImm timm:$imm))>;
}
@@ -7207,12 +7207,12 @@ let Predicates = [HasAVX1Only] in {
// VINSERTF128 - Insert packed floating-point values
//
let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
-def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
+def VINSERTF128rri : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
(ins VR256:$src1, VR128:$src2, u8imm:$src3),
"vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[]>, Sched<[WriteFShuffle256]>, VEX, VVVV, VEX_L;
let mayLoad = 1 in
-def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
+def VINSERTF128rmi : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
(ins VR256:$src1, f128mem:$src2, u8imm:$src3),
"vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[]...
[truncated]
|
|
@llvm/pr-subscribers-backend-x86 Author: Simon Pilgrim (RKSimon) ChangesMakes it easier to algorithmically recreate the instruction name in various analysis scripts I'm working on Patch is 71.31 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/108593.diff 31 Files Affected:
diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
index 2fb499122fbbfb..d2ee0f1bac6831 100644
--- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
@@ -1255,16 +1255,16 @@ bool X86InstructionSelector::selectExtract(MachineInstr &I,
if (SrcTy.getSizeInBits() == 256 && DstTy.getSizeInBits() == 128) {
if (HasVLX)
- I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr));
+ I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rri));
else if (HasAVX)
- I.setDesc(TII.get(X86::VEXTRACTF128rr));
+ I.setDesc(TII.get(X86::VEXTRACTF128rri));
else
return false;
} else if (SrcTy.getSizeInBits() == 512 && HasAVX512) {
if (DstTy.getSizeInBits() == 128)
- I.setDesc(TII.get(X86::VEXTRACTF32x4Zrr));
+ I.setDesc(TII.get(X86::VEXTRACTF32x4Zrri));
else if (DstTy.getSizeInBits() == 256)
- I.setDesc(TII.get(X86::VEXTRACTF64x4Zrr));
+ I.setDesc(TII.get(X86::VEXTRACTF64x4Zrri));
else
return false;
} else
@@ -1388,16 +1388,16 @@ bool X86InstructionSelector::selectInsert(MachineInstr &I,
if (DstTy.getSizeInBits() == 256 && InsertRegTy.getSizeInBits() == 128) {
if (HasVLX)
- I.setDesc(TII.get(X86::VINSERTF32x4Z256rr));
+ I.setDesc(TII.get(X86::VINSERTF32x4Z256rri));
else if (HasAVX)
- I.setDesc(TII.get(X86::VINSERTF128rr));
+ I.setDesc(TII.get(X86::VINSERTF128rri));
else
return false;
} else if (DstTy.getSizeInBits() == 512 && HasAVX512) {
if (InsertRegTy.getSizeInBits() == 128)
- I.setDesc(TII.get(X86::VINSERTF32x4Zrr));
+ I.setDesc(TII.get(X86::VINSERTF32x4Zrri));
else if (InsertRegTy.getSizeInBits() == 256)
- I.setDesc(TII.get(X86::VINSERTF64x4Zrr));
+ I.setDesc(TII.get(X86::VINSERTF64x4Zrri));
else
return false;
} else
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
index 9cc72d32d85f94..ca6b82cd0f1e6f 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
@@ -1158,13 +1158,13 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
DestName = getRegName(MI->getOperand(0).getReg());
break;
- case X86::VPERM2F128rr:
- case X86::VPERM2I128rr:
+ case X86::VPERM2F128rri:
+ case X86::VPERM2I128rri:
Src2Name = getRegName(MI->getOperand(2).getReg());
[[fallthrough]];
- case X86::VPERM2F128rm:
- case X86::VPERM2I128rm:
+ case X86::VPERM2F128rmi:
+ case X86::VPERM2I128rmi:
// For instruction comments purpose, assume the 256-bit vector is v4i64.
if (MI->getOperand(NumOperands - 1).isImm())
DecodeVPERM2X128Mask(4, MI->getOperand(NumOperands - 1).getImm(),
diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp
index 7343af1bdc9a5a..a909440f983173 100644
--- a/llvm/lib/Target/X86/X86CompressEVEX.cpp
+++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp
@@ -138,8 +138,8 @@ static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) {
case X86::VSHUFI32X4Z256rri:
case X86::VSHUFI64X2Z256rmi:
case X86::VSHUFI64X2Z256rri: {
- assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
- NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
+ assert((NewOpc == X86::VPERM2F128rri || NewOpc == X86::VPERM2I128rri ||
+ NewOpc == X86::VPERM2F128rmi || NewOpc == X86::VPERM2I128rmi) &&
"Unexpected new opcode!");
MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
int64_t ImmVal = Imm.getImm();
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index c9885242131238..a9ee128bf54cfc 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -368,7 +368,7 @@ multiclass vinsert_for_size_split<int Opcode, X86VectorVTInfo From,
SDPatternOperator vinsert_for_mask,
X86FoldableSchedWrite sched> {
let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
- defm rr : AVX512_maskable_split<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
+ defm rri : AVX512_maskable_split<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
(ins To.RC:$src1, From.RC:$src2, u8imm:$src3),
"vinsert" # From.EltTypeName # "x" # From.NumElts,
"$src3, $src2, $src1", "$src1, $src2, $src3",
@@ -380,7 +380,7 @@ multiclass vinsert_for_size_split<int Opcode, X86VectorVTInfo From,
(iPTR imm))>,
AVX512AIi8Base, EVEX, VVVV, Sched<[sched]>;
let mayLoad = 1 in
- defm rm : AVX512_maskable_split<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
+ defm rmi : AVX512_maskable_split<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
(ins To.RC:$src1, From.MemOp:$src2, u8imm:$src3),
"vinsert" # From.EltTypeName # "x" # From.NumElts,
"$src3, $src2, $src1", "$src1, $src2, $src3",
@@ -408,7 +408,7 @@ multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
let Predicates = p in {
def : Pat<(vinsert_insert:$ins
(To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
- (To.VT (!cast<Instruction>(InstrStr#"rr")
+ (To.VT (!cast<Instruction>(InstrStr#"rri")
To.RC:$src1, From.RC:$src2,
(INSERT_get_vinsert_imm To.RC:$ins)))>;
@@ -416,7 +416,7 @@ multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
(To.VT To.RC:$src1),
(From.VT (From.LdFrag addr:$src2)),
(iPTR imm)),
- (To.VT (!cast<Instruction>(InstrStr#"rm")
+ (To.VT (!cast<Instruction>(InstrStr#"rmi")
To.RC:$src1, addr:$src2,
(INSERT_get_vinsert_imm To.RC:$ins)))>;
}
@@ -529,7 +529,7 @@ let Predicates = p in {
(From.VT From.RC:$src2),
(iPTR imm))),
Cast.RC:$src0)),
- (!cast<Instruction>(InstrStr#"rrk")
+ (!cast<Instruction>(InstrStr#"rrik")
Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
(INSERT_get_vinsert_imm To.RC:$ins))>;
def : Pat<(Cast.VT
@@ -541,7 +541,7 @@ let Predicates = p in {
(From.LdFrag addr:$src2))),
(iPTR imm))),
Cast.RC:$src0)),
- (!cast<Instruction>(InstrStr#"rmk")
+ (!cast<Instruction>(InstrStr#"rmik")
Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, addr:$src2,
(INSERT_get_vinsert_imm To.RC:$ins))>;
@@ -552,7 +552,7 @@ let Predicates = p in {
(From.VT From.RC:$src2),
(iPTR imm))),
Cast.ImmAllZerosV)),
- (!cast<Instruction>(InstrStr#"rrkz")
+ (!cast<Instruction>(InstrStr#"rrikz")
Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
(INSERT_get_vinsert_imm To.RC:$ins))>;
def : Pat<(Cast.VT
@@ -562,7 +562,7 @@ let Predicates = p in {
(From.VT (From.LdFrag addr:$src2)),
(iPTR imm))),
Cast.ImmAllZerosV)),
- (!cast<Instruction>(InstrStr#"rmkz")
+ (!cast<Instruction>(InstrStr#"rmikz")
Cast.KRCWM:$mask, To.RC:$src1, addr:$src2,
(INSERT_get_vinsert_imm To.RC:$ins))>;
}
@@ -677,7 +677,7 @@ multiclass vextract_for_size_split<int Opcode,
SchedWrite SchedRR, SchedWrite SchedMR> {
let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
- defm rr : AVX512_maskable_split<Opcode, MRMDestReg, To, (outs To.RC:$dst),
+ defm rri : AVX512_maskable_split<Opcode, MRMDestReg, To, (outs To.RC:$dst),
(ins From.RC:$src1, u8imm:$idx),
"vextract" # To.EltTypeName # "x" # To.NumElts,
"$idx, $src1", "$src1, $idx",
@@ -685,7 +685,7 @@ multiclass vextract_for_size_split<int Opcode,
(vextract_for_mask:$idx (From.VT From.RC:$src1), (iPTR imm))>,
AVX512AIi8Base, EVEX, Sched<[SchedRR]>;
- def mr : AVX512AIi8<Opcode, MRMDestMem, (outs),
+ def mri : AVX512AIi8<Opcode, MRMDestMem, (outs),
(ins To.MemOp:$dst, From.RC:$src1, u8imm:$idx),
"vextract" # To.EltTypeName # "x" # To.NumElts #
"\t{$idx, $src1, $dst|$dst, $src1, $idx}",
@@ -695,7 +695,7 @@ multiclass vextract_for_size_split<int Opcode,
Sched<[SchedMR]>;
let mayStore = 1, hasSideEffects = 0 in
- def mrk : AVX512AIi8<Opcode, MRMDestMem, (outs),
+ def mrik : AVX512AIi8<Opcode, MRMDestMem, (outs),
(ins To.MemOp:$dst, To.KRCWM:$mask,
From.RC:$src1, u8imm:$idx),
"vextract" # To.EltTypeName # "x" # To.NumElts #
@@ -718,12 +718,12 @@ multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> {
let Predicates = p in {
def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
- (To.VT (!cast<Instruction>(InstrStr#"rr")
+ (To.VT (!cast<Instruction>(InstrStr#"rri")
From.RC:$src1,
(EXTRACT_get_vextract_imm To.RC:$ext)))>;
def : Pat<(store (To.VT (vextract_extract:$ext (From.VT From.RC:$src1),
(iPTR imm))), addr:$dst),
- (!cast<Instruction>(InstrStr#"mr") addr:$dst, From.RC:$src1,
+ (!cast<Instruction>(InstrStr#"mri") addr:$dst, From.RC:$src1,
(EXTRACT_get_vextract_imm To.RC:$ext))>;
}
}
@@ -828,31 +828,31 @@ defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v32bf16_info, v16bf16x_info,
// smaller extract to enable EVEX->VEX.
let Predicates = [NoVLX, HasEVEX512] in {
def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))),
- (v2i64 (VEXTRACTI128rr
+ (v2i64 (VEXTRACTI128rri
(v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))),
- (v2f64 (VEXTRACTF128rr
+ (v2f64 (VEXTRACTF128rri
(v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))),
- (v4i32 (VEXTRACTI128rr
+ (v4i32 (VEXTRACTI128rri
(v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))),
- (v4f32 (VEXTRACTF128rr
+ (v4f32 (VEXTRACTF128rri
(v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))),
- (v8i16 (VEXTRACTI128rr
+ (v8i16 (VEXTRACTI128rri
(v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v8f16 (extract_subvector (v32f16 VR512:$src), (iPTR 8))),
- (v8f16 (VEXTRACTF128rr
+ (v8f16 (VEXTRACTF128rri
(v16f16 (EXTRACT_SUBREG (v32f16 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
- (v16i8 (VEXTRACTI128rr
+ (v16i8 (VEXTRACTI128rri
(v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
(iPTR 1)))>;
}
@@ -861,31 +861,31 @@ def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
// smaller extract to enable EVEX->VEX.
let Predicates = [HasVLX] in {
def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))),
- (v2i64 (VEXTRACTI32x4Z256rr
+ (v2i64 (VEXTRACTI32x4Z256rri
(v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))),
- (v2f64 (VEXTRACTF32x4Z256rr
+ (v2f64 (VEXTRACTF32x4Z256rri
(v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))),
- (v4i32 (VEXTRACTI32x4Z256rr
+ (v4i32 (VEXTRACTI32x4Z256rri
(v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))),
- (v4f32 (VEXTRACTF32x4Z256rr
+ (v4f32 (VEXTRACTF32x4Z256rri
(v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))),
- (v8i16 (VEXTRACTI32x4Z256rr
+ (v8i16 (VEXTRACTI32x4Z256rri
(v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v8f16 (extract_subvector (v32f16 VR512:$src), (iPTR 8))),
- (v8f16 (VEXTRACTF32x4Z256rr
+ (v8f16 (VEXTRACTF32x4Z256rri
(v16f16 (EXTRACT_SUBREG (v32f16 VR512:$src), sub_ymm)),
(iPTR 1)))>;
def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
- (v16i8 (VEXTRACTI32x4Z256rr
+ (v16i8 (VEXTRACTI32x4Z256rri
(v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
(iPTR 1)))>;
}
@@ -904,7 +904,7 @@ let Predicates = p in {
(To.VT (vextract_extract:$ext
(From.VT From.RC:$src), (iPTR imm)))),
To.RC:$src0)),
- (Cast.VT (!cast<Instruction>(InstrStr#"rrk")
+ (Cast.VT (!cast<Instruction>(InstrStr#"rrik")
Cast.RC:$src0, Cast.KRCWM:$mask, From.RC:$src,
(EXTRACT_get_vextract_imm To.RC:$ext)))>;
@@ -913,7 +913,7 @@ let Predicates = p in {
(To.VT (vextract_extract:$ext
(From.VT From.RC:$src), (iPTR imm)))),
Cast.ImmAllZerosV)),
- (Cast.VT (!cast<Instruction>(InstrStr#"rrkz")
+ (Cast.VT (!cast<Instruction>(InstrStr#"rrikz")
Cast.KRCWM:$mask, From.RC:$src,
(EXTRACT_get_vextract_imm To.RC:$ext)))>;
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 401b8ce71edaf5..0a159db91ff5a2 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -2597,8 +2597,8 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
.setImm(X86::getSwappedVCMPImm(
MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f));
break;
- case X86::VPERM2F128rr:
- case X86::VPERM2I128rr:
+ case X86::VPERM2F128rri:
+ case X86::VPERM2I128rri:
// Flip permute source immediate.
// Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
// Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
@@ -6258,16 +6258,16 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
case X86::VMOVAPSZ128mr_NOVLX:
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
- get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
+ get(X86::VEXTRACTF32x4Zmri), X86::sub_xmm);
case X86::VMOVUPSZ128mr_NOVLX:
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
- get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
+ get(X86::VEXTRACTF32x4Zmri), X86::sub_xmm);
case X86::VMOVAPSZ256mr_NOVLX:
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
- get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
+ get(X86::VEXTRACTF64x4Zmri), X86::sub_ymm);
case X86::VMOVUPSZ256mr_NOVLX:
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
- get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
+ get(X86::VEXTRACTF64x4Zmri), X86::sub_ymm);
case X86::MOV32ri64: {
Register Reg = MIB.getReg(0);
Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
@@ -6775,8 +6775,8 @@ static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
case X86::VPACKUSWBZ128rr:
case X86::VPACKSSDWZ128rr:
case X86::VPACKUSDWZ128rr:
- case X86::VPERM2F128rr:
- case X86::VPERM2I128rr:
+ case X86::VPERM2F128rri:
+ case X86::VPERM2I128rri:
case X86::VSHUFF32X4Z256rri:
case X86::VSHUFF32X4Zrri:
case X86::VSHUFF64X2Z256rri:
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 4e5f2e3f872ad4..278ae9a09d45d6 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -7164,11 +7164,11 @@ let Predicates = [HasAVXNECONVERT, NoVLX] in
let ExeDomain = SSEPackedSingle in {
let isCommutable = 1 in
-def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
+def VPERM2F128rri : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
(ins VR256:$src1, VR256:$src2, u8imm:$src3),
"vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", []>,
VEX, VVVV, VEX_L, Sched<[WriteFShuffle256]>;
-def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
+def VPERM2F128rmi : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
(ins VR256:$src1, f256mem:$src2, u8imm:$src3),
"vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", []>,
VEX, VVVV, VEX_L, Sched<[WriteFShuffle256.Folded, WriteFShuffle256.ReadAfterFold]>;
@@ -7181,12 +7181,12 @@ def Perm2XCommuteImm : SDNodeXForm<timm, [{
multiclass vperm2x128_lowering<string InstrStr, ValueType VT, PatFrag memop_frag> {
def : Pat<(VT (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 timm:$imm))),
- (!cast<Instruction>(InstrStr#rr) VR256:$src1, VR256:$src2, timm:$imm)>;
+ (!cast<Instruction>(InstrStr#rri) VR256:$src1, VR256:$src2, timm:$imm)>;
def : Pat<(VT (X86VPerm2x128 VR256:$src1, (memop_frag addr:$src2), (i8 timm:$imm))),
- (!cast<Instruction>(InstrStr#rm) VR256:$src1, addr:$src2, timm:$imm)>;
+ (!cast<Instruction>(InstrStr#rmi) VR256:$src1, addr:$src2, timm:$imm)>;
// Pattern with load in other operand.
def : Pat<(VT (X86VPerm2x128 (memop_frag addr:$src2), VR256:$src1, (i8 timm:$imm))),
- (!cast<Instruction>(InstrStr#rm) VR256:$src1, addr:$src2,
+ (!cast<Instruction>(InstrStr#rmi) VR256:$src1, addr:$src2,
(Perm2XCommuteImm timm:$imm))>;
}
@@ -7207,12 +7207,12 @@ let Predicates = [HasAVX1Only] in {
// VINSERTF128 - Insert packed floating-point values
//
let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
-def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
+def VINSERTF128rri : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
(ins VR256:$src1, VR128:$src2, u8imm:$src3),
"vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[]>, Sched<[WriteFShuffle256]>, VEX, VVVV, VEX_L;
let mayLoad = 1 in
-def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
+def VINSERTF128rmi : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
(ins VR256:$src1, f128mem:$src2, u8imm:$src3),
"vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[]...
[truncated]
|
…instruction names Makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm working on
RKSimon
force-pushed
the
x86-subvector-rename
branch
from
46e6d72 to
4db34cb
Compare
phoebewang
added a commit
to phoebewang/llvm-project
that referenced
this pull request
Sep 26, 2024
phoebewang
added a commit
that referenced
this pull request
Sep 26, 2024
Sterling-Augustine
pushed a commit
to Sterling-Augustine/llvm-project
that referenced
this pull request
Sep 27, 2024
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm working on